Quantum FIREBALL PLUS AS 10.2 Product Manual Download

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Quantum Fireball Plus AS

10.2/20.5/30.0/40.0/60.0 GB AT

Product Manual

December 12, 2000

81-121729-04

Summary of Contents for FIREBALL PLUS AS 10.2

Page 1: ...m Fireball Plus AS Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT 10 2 20 5 30 0 40 0 60 0 GB AT 10 2 20 5 30 0 40 0 60 0 GB AT 10 2 20 5 30 0 40 0 60 0 GB AT Product Manual Product Manual Product Manual Product Manual December 12 2000 81 121729 04 ...

Page 2: ...52 4 703 176 4 730 321 4 772 974 4 783 705 4 819 153 4 882 671 4 920 442 4 920 434 4 982 296 5 005 089 5 027 241 5 031 061 5 084 791 5 119 254 5 160 865 5 170 229 5 177 771 Other U S and Foreign Patents Pending 2000 Quantum Corporation All rights reserved Printed in U S A Quantum the Quantum logo and AIRLOCK are trademarks of Quantum Corporation registered in the U S A and other countries Capacity...

Page 3: ...3 3 1 Cable Select CS Jumper 3 5 3 3 2 Drive Select DS Jumper 3 6 3 3 3 Master Jumper configuration 3 6 3 3 4 Jumper Parking PK Position 3 6 3 3 5 Alternate Capacity AC 3 7 3 4 ATA BUS ADAPTER 3 8 3 4 1 40 Pin ATA Bus Connector 3 8 3 4 2 Adapter Board 3 8 3 5 MOUNTING 3 9 3 5 1 Orientation 3 9 3 5 2 Clearance 3 11 3 5 3 Ventilation 3 11 3 6 COMBINATION CONNECTOR J1 3 11 3 6 1 DC Power J1 Section A...

Page 4: ... 4 10 4 11 RELIABILITY 4 10 4 12 ELECTROMAGNETIC SUSCEPTIBILITY 4 11 4 13 SPINDLE IMBALANCE 4 11 4 14 DISK ERRORS 4 11 Chapter 5 BASIC PRINCIPLES OF OPERATION 5 1 Quantum Fireball Plus AS DRIVE MECHANISM 5 1 5 1 1 Base Casting Assembly 5 3 5 1 2 DC Motor Assembly 5 3 5 1 3 Disk Stack Assemblies 5 3 5 1 4 Headstack Assembly 5 4 5 1 5 Rotary Positioner Assembly 5 4 5 1 6 Automatic Actuator Lock 5 4 ...

Page 5: ... Sectors 6 31 6 7 4 Read Verify Sectors 6 32 6 7 5 Seek 6 33 6 7 6 Execute Drive Diagnostics 6 34 6 7 7 INITIALIZE DRIVE PARAMETERS 6 36 6 7 8 Download Microcode 6 37 6 7 9 SMART 6 38 6 7 10 Read Multiple Sectors 6 48 6 7 11 Write Multiple Sectors 6 49 6 7 12 Set Multiple Mode 6 50 6 7 13 Read DMA 6 51 6 7 14 Write DMA 6 52 6 7 15 STANDBY IMMEDIATE 6 54 6 7 16 IDLE IMMEDIATE 6 55 6 7 17 STANDBY 6 ...

Page 6: ...Figure 3 10 Drive Power Supply and ATA Bus Interface Cables 3 14 Figure 3 11 Completing the Drive Installation 3 15 Figure 5 1 Quantum Fireball Plus AS AT Hard Disk Drive Exploded View 5 2 Figure 5 2 Quantum Fireball Plus AS AT Hard Disk Drive Block Diagram 5 5 Figure 5 3 Block Diagram 5 6 Figure 5 4 Sector Data Field with ECC Check Bytes 5 14 Figure 6 1 PIO Interface Timing 6 10 Figure 6 2 Multiw...

Page 7: ...10 Table 6 6 Multiword DMA Host Interface Timing 6 11 Table 6 7 Ultra DMA Data Transfer Timing Requirements 6 12 Table 6 8 Ultra DMA Data Burst Timing Descriptions 6 13 Table 6 9 Host Interface RESET Timing 6 20 Table 6 10 I O Port Functions and Selection Addresses 6 21 Table 6 11 Command Block Register Initial Values 6 22 Table 6 12 Device Control Register Bits 6 23 Table 6 13 Drive Address Regis...

Page 8: ... 6 74 Table 6 29 DEFECT ENTRY DATA FORMAT 6 74 Table 6 30 Accessing the READ CONFIGURATION Command 6 75 Table 6 31 Accessing the SET CONFIGURATION Command 6 76 Table 6 32 Accessing the SET CONFIGURATION WITHOUT SAVING TO DISK Command 6 77 Table 6 33 Configuration Command Format 6 78 Table 6 34 Command Errors 6 86 ...

Page 9: ...ation principles of operation interface command implementation and maintenance 1 2 1 2 1 2 1 2 MANUAL ORGANIZATION MANUAL ORGANIZATION MANUAL ORGANIZATION MANUAL ORGANIZATION This manual is organized into the following chapters Chapter 1 About This Manual Chapter 2 General Description Chapter 3 Installation Chapter 4 Specifications Chapter 5 Basic Principles of Operation Chapter 6 ATA Bus Interfac...

Page 10: ...hat table Typographical Conventions Names of Bits Bit names are presented in initial capitals An example is the Host Software Reset bit Commands Interface commands are listed in all capitals An example is WRITE LONG Register Names Registers are given in this manual with initial capitals An example is the Alternate Status Register Parameters Parameters are given as initial capitals when spelled out...

Page 11: ...t Computer Voice This refers to items you type at the computer keyboard These items are listed in 10 point all capitals Courier font An example is FORMAT C S 1 4 1 4 1 4 1 4 REFERENCES REFERENCES REFERENCES REFERENCES For additional information about the AT interface refer to IBM Technical Reference Manual 6183355 March 1986 ATA Common Access Method Specification Revision 5 0 ...

Page 12: ...About This Manual 1 4 Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT ...

Page 13: ...ve controller and use ATA commands to optimize system performance Because the drive manages media defects and error recovery internally these operations are fully transparent to the user The innovative design of the Quantum Fireball Plus AS hard disk drives incorporate leading edge technologies such as Ultra ATA 100 Advanced Cache Management Shock Protection System SPS Data Protection System DPS a...

Page 14: ...word DMA mode 2 and Ultra DMA modes 0 1 2 3 4 and 5 Adaptive cache segmentation Reliability 625 000 hours mean time between failure MTBF in the field Automatic retry on read errors 344 bit interleaved Reed Solomon Error Correcting Code ECC with cross checking correction up to four separate bursts of 32 bits each totalling up to 128 bits in length S M A R T 4 Self Monitoring Analysis and Reporting ...

Page 15: ...lifications Product EMI EMS Qualifications Product EMI EMS Qualifications Product EMI EMS Qualifications CE Mark authorization is granted by TUV Rheinland in compliance with our qualifying under EN 55022 1994 and EN 50082 1 1997 C Tick Mark is an Australian authorization marked noted on Quantum s disk drive products The mark proves conformity to the regulatory compliance document AS NZS 3548 1995 ...

Page 16: ...General Description 2 8 Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT ...

Page 17: ...also explains how to start up and operate the drive 3 1 3 1 3 1 3 1 SPACE REQUIREMENTS SPACE REQUIREMENTS SPACE REQUIREMENTS SPACE REQUIREMENTS The Quantum Fireball Plus AS hard disk drives are shipped without a faceplate Figure 3 1 shows the external dimensions of the Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT drives Figure 3 1 Figure 3 1 Figure 3 1 Figure 3 1 Mechanical Dimensions o...

Page 18: ...gure 3 2 Figure 3 2 Figure 3 2 Drive Packing Assembly CAUTION CAUTION CAUTION CAUTION The maximum limits for physical shock can be exceeded if the drive is not handled properly Special care should be taken not to bump or drop the drive It is highly recommended that Quantum Fireball Plus AS drives are not stacked or placed on any hard surface after they are unpacked Such handling could cause media ...

Page 19: ...ure 3 3 Drive Packing Assembly of a Polypropylene 20 Pack Container Note The 20 pack container should be shipped in the same way it was received from Quantum When individual drives are shipped from the 20 pack container then it should be appropri ately packaged not supplied with the 20 pack to prevent dam age ...

Page 20: ...e installed This section describes the hardware options that you must take into account prior to installation Figure 3 4 shows the printed circuit board PCB assembly indicating the jumpers that control some of these options Figure 3 4 Figure 3 4 Figure 3 4 Figure 3 4 Jumper Locations for the Quantum Fireball Plus AS Hard Disk Drive Figure 3 5 Figure 3 5 Figure 3 5 Figure 3 5 Jumper Locations on th...

Page 21: ...her they can be configured as Master or Slave either by the CS or DS jumpers To configure the drive as a Master or Slave with the CS feature the CS jumper is installed 1 The drive s position on the 80 conductor Ultra ATA data cable then determines whether the drive is a Master Device 0 or a Slave Device 1 If the drive is connected to the end of the Ultra cable Select data cable the drive is a Mast...

Page 22: ...d To configure a drive as the Master Device 0 a jumper must be installed on the DS pins Note The order in which drives are connected in a daisy chain has no significance 3 3 3 3 3 3 3 3 3 3 3 3 Master Jumper configuration Master Jumper configuration Master Jumper configuration Master Jumper configuration In combination with the current DS or CS jumper settings the Slave Present SP jumper can be im...

Page 23: ...addressing to use the full capacity A summary of these effects for the Quantum Fireball Plus AS drives is shown in the following table Figure 3 6 Figure 3 6 Figure 3 6 Figure 3 6 AT Connector and Jumper Location AC JUMPER OUT AC JUMPER OUT AC JUMPER OUT AC JUMPER OUT AC JUMPER IN AC JUMPER IN AC JUMPER IN AC JUMPER IN 10 GB 10 GB 10 GB 10 GB C 16 383 H 16 S 63 LBA 20 075 548 C 16 383 H 15 S 63 LBA...

Page 24: ...um Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT hard disk drives If the motherboard has an ATA connector simply connect a 40 pin ribbon cable between the drive and the motherboard You should also refer to the motherboard instruction manual and refer to Chapter 6 of this manual to ensure signal compatibility 3 4 2 3 4 2 3 4 2 3 4 2 Adapter Board Adapter Board Adapter Board Adapter Board If your ...

Page 25: ... show the location of the three mounting holes on each side of the drive The drive can also be mounted using the four mounting hole locations on the PCB side of the drive Note It is highly recommended that the drive is hard mounted on to the chassis of the system being used for general operation as well as for test purposes Failure to hard mount the drive can result in erroneous errors during test...

Page 26: ... holes Do not ex ceed the specified length for the mounting screws The specified screw length allows full use of the mounting hole threads while avoiding damaging or placing un wanted stress on the PCB Figure 3 8 specifies the min imum clearance between the PCB and the screws in the mounting holes To avoid stripping the mounting hole threads the maximum torque applied to the screws must not exceed...

Page 27: ... air temperature does not exceed 131 F 55 C at any point along the drive form factor envelope 3 6 3 6 3 6 3 6 COMBINATION CONNECTOR J1 COMBINATION CONNECTOR J1 COMBINATION CONNECTOR J1 COMBINATION CONNECTOR J1 J1 is a three in one combination connector The drive s DC power can be applied to section A The ATA bus interface 40 pin uses section C The connector is mounted on the back edge of the print...

Page 28: ...ector J1 Section C ATA Bus Interface Connector J1 Section C On the Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT hard disk drives the ATA bus interface cable connector J1 section C is a 40 pin Universal Header as shown in Figure 3 9 To prevent the possibility of incorrect installation the connector has been keyed by removing Pin 20 This ensures that a connector cannot be installed upside...

Page 29: ...all Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT hard disk drive in an AT compatible system without a 40 pin ATA bus connector on its motherboard you need a third party IDE compatible adapter board 3 8 1 3 8 1 3 8 1 3 8 1 Adapter Board Installation Adapter Board Installation Adapter Board Installation Adapter Board Installation Carefully read the manual that accompanies your adapter board before install...

Page 30: ... To connect the drive to the board 1 Insert the 40 pin cable connector into the mating connector of the adapter board Make sure that pin 1 of the connector matches with pin 1 on the cable 2 Insert the other end of the cable into the header on the drive When inserting this end of the cable make sure that pin 1 of the cable connects to pin 1 of the drive connector 3 Secure the drive to the system ch...

Page 31: ...er Older BIOS that only support Int 13 commands for accessing ATA drives through DOS based operating systems will be limited to use only 1024 cylinders This will reduce the effective capacity of the drive to 528 Mbytes Whenever possible the Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT drive should be used on systems that support LBA translation to ensure the use of the entire capacity o...

Page 32: ... not possible the following are some techniques that can be used to overcome this barrier Use a third party software that supplements the BIOS and adds Int 13 extension support Obtain a BIOS upgrade from the system board manufacturer Many system board manufacturers allow their BIOS to be upgraded in the field using special download utilities Information on BIOS upgrades can be obtained on the Syst...

Page 33: ...hard disk drives The drive supports the translation of its physical drive geometry parameters such as cylinders heads and sectors per track to a logical addressing mode The drive can work with different BIOS drive type tables of the various host systems You can choose any drive type that does not exceed the capacity of the drive Table 3 3 gives the logical parameters that provide the maximum capac...

Page 34: ...es the number of cylinders heads and sectors for a particular drive type You must choose a drive type that meets the following requirements For the 10 2 GB 20 5 GB 30 0 GB 40 0 GB 60 0 GB Logical Cylinders x Logical Heads x Logical Sectors Track x 512 8 455 200 768 4 Boot the system using the operating system installation disk for example MS DOS then follow the installation instructions in the ope...

Page 35: ...0 0 GB 40 0 GB 40 0 GB 40 0 GB 40 0 GB 60 0 GB 60 0 GB 60 0 GB 60 0 GB Formatted Capacity 10 273 MB 20 547 MB 30 020 MB 40 027 MB 60 040 MB Nominal rotational speed rpm 7 200 7 200 7 200 7 200 7 200 Number of Disks 1 1 2 2 3 Number of R W heads 1 2 3 4 6 Data Organization Zones per surface 15 15 15 15 15 Tracks per surface 35 136 35 136 35 136 35 136 35 136 Total tracks 35 136 70 272 105 408 140 5...

Page 36: ... sec minimum 471 Mb sec maximum 252 Mb sec minimum 471 Mb sec maximum 252 Mb sec minimum 471 Mb sec maximum 252 Mb sec minimum 471 Mb sec maximum Read Buffer to ATA Bus PIO Mode with IORDY 16 7 MB sec maximum 16 7 MB sec maximum 16 7 MB sec maximum 16 7 MB sec maximum 16 7 MB sec maximum Read Buffer to ATA Bus Ultra ATA Mode 100 MB sec maximum 100 MB sec maximum 100 MB sec maximum 100 MB sec maxim...

Page 37: ... Note The AT capacity is artificially limited to a 2 1 GB partition boundary 4 3 4 3 4 3 4 3 DATA TRANSFER RATES DATA TRANSFER RATES DATA TRANSFER RATES DATA TRANSFER RATES Data is transferred from the disk to the read buffer at a rate of up to 471 Mb s in bursts Data is transferred from the read buffer to the ATA bus at a rate of up to 16 7 MB s using programmed I O with IORDY or at a rate of up ...

Page 38: ...e to when the drive is ready to accept any command 6 Drive Ready is the condition in which the disks are rotating at the rated speed and the drive is able to accept and execute commands requiring disk access without further delay at power or start up Error recovery routines may extend the time to as long as 45 seconds for drive ready 7 Standby is the condition at which the microprocessor is powere...

Page 39: ... be lost in the sector being written at the time of power loss The drive can withstand transient voltages of 10 to 100 from nominal while powering up or down 4 5 2 4 5 2 4 5 2 4 5 2 Power Reset Limits Power Reset Limits Power Reset Limits Power Reset Limits When powering up the drive remains reset inactive until both rising voltage thresholds reset limits are exceeded for 30 ms When powering down ...

Page 40: ...20 5 10 2 20 5 10 2 20 5 10 2 20 5 GB GB GB GB 1 Disk 1 Disk 1 Disk 1 Disk 30 0 30 0 30 0 30 0 40 0GB 40 0GB 40 0GB 40 0GB 2 Disks 2 Disks 2 Disks 2 Disks 60 0 GB 60 0 GB 60 0 GB 60 0 GB 3 Disks 3 Disks 3 Disks 3 Disks 10 2 20 5 10 2 20 5 10 2 20 5 10 2 20 5 GB GB GB GB 1 Disk 1 Disk 1 Disk 1 Disk 30 0 30 0 30 0 30 0 40 0GB 40 0GB 40 0GB 40 0GB 2 Disks 2 Disks 2 Disks 2 Disks 60 0 GB 60 0 GB 60 0 ...

Page 41: ... the acoustical characteristics of the Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT hard disk drive The acoustics are measured in an anechoic chamber with background noise at least 10dBA less than the expected sound pressure Lp A To distinguish between sound power and sound pressure standards sound power Lw A is specified in Bels The relationship between bels and dBA for sound power is ...

Page 42: ...ive form factor envelope Airflow or other means must be used as needed to meet this requirement 2 The humidity range shown is applicable for temperatures whose combination does not result in condensation in violation of the wet bulb specifications 3 Altitude is relative to sea level 4 The specified drive uncorrectable error rate will not be exceeded over these conditions PARAMETER PARAMETER PARAME...

Page 43: ...es can withstand a drop from 30 inches onto a concrete surface on any of its surfaces six edges or three corners The 20 pack shipping container can withstand a drop from 30 inches onto a concrete surface on any of its surfaces six edges or three corners Table 4 8 Table 4 8 Table 4 8 Table 4 8 Shock and Vibration Specifications 1 The specified drive unrecovered error rate will not be exceeded over ...

Page 44: ...h is strongly recommended Always keep the drive inside its special antistatic bag until ready to install Note To avoid causing any damage to the drive do not touch the Printed Circuit Board PCB or any of its components when handling the drive 4 11 4 11 4 11 4 11 RELIABILITY RELIABILITY RELIABILITY RELIABILITY Mean Time Between Failures MTBF The projected field MTBF is 625 000 hours The Quantum MTB...

Page 45: ...onsidered recovered read errors Read on arrival is disabled to meet this specification Errors corrected by the thermal asperity correction are not considered recovered read errors 2 Unrecovered read errors are errors that are not correctable using ECC or retries The drive terminates retry reads either when a repeating error pattern occurs or after the programmed limit for unsuccessful retries and ...

Page 46: ...QUANTUM FIREBALL PLUS AS DRIVE MECHANISM This section describes the drive mechanism Section 5 2 describes the drive electronics The Quantum Fireball Plus AS hard disk drives consist of a mechanical assembly and a PCB as shown in Figure 5 1 The head disk assembly HDA contains the mechanical subassemblies of the drive which are sealed under a metal cover The HDA consists of the following components ...

Page 47: ...Basic Principles of Operation Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT 5 2 Figure 5 1 Figure 5 1 Figure 5 1 Figure 5 1 Quantum Fireball Plus AS AT Hard Disk Drive Exploded View ...

Page 48: ...disks secured by a disk clamp The aluminum alloy disks have a sputtered thin film magnetic coating A carbon overcoat lubricates the disk surface This prevents head and media wear due to head contact with the disk surface during head takeoff and landing Head contact with the disk surface occurs only in the landing zone outside of the data area when the disk is not rotating at full speed The landing...

Page 49: ...h stop prevents the heads from being driven into the spindle or off the disk surface Current from the power amplifier induces a magnetic field in the voice coil Fluctuations in the field around the permanent magnet cause the voice coil to move The movement of the voice coil positions the heads over the requested cylinder 5 1 6 5 1 6 5 1 6 5 1 6 Automatic Actuator Lock Automatic Actuator Lock Autom...

Page 50: ...lter 5 2 5 2 5 2 5 2 DRIVE ELECTRONICS DRIVE ELECTRONICS DRIVE ELECTRONICS DRIVE ELECTRONICS Advanced circuit Very Large Scale Integration design and the use of miniature surface mounted devices and proprietary VLSI components enable the drive electronics including the ATA bus interface to reside on a single printed circuit board assembly PCBA Figure 5 2 contains a simplified block diagram of the ...

Page 51: ...sk Controller and ATA Interface Integrated µProcessor Disk Controller and ATA Interface Integrated µProcessor Disk Controller and ATA Interface Electronics Electronics Electronics Electronics The µProcessor Disk Controller and ATA Interface electronics are contained in a proprietary ASIC developed by Quantum as shown below in Figure 5 3 Figure 5 3 Figure 5 3 Figure 5 3 Figure 5 3 Block Diagram ...

Page 52: ...ad write channel process timing and position information and stores it in registers that are read by the servo firmware 5 2 1 3 5 2 1 3 5 2 1 3 5 2 1 3 Error Correction Code ECC Control Error Correction Code ECC Control Error Correction Code ECC Control Error Correction Code ECC Control The Error Correction Code ECC Control block utilizes a Reed Solomon encoder decoder circuit that is used for dis...

Page 53: ...ad Write Interface Read Write Interface The Read Write interface allows the integrated µprocessor disk controller to communicate with the Read Write chip 5 2 1 8 5 2 1 8 5 2 1 8 5 2 1 8 ATA Interface Controller ATA Interface Controller ATA Interface Controller ATA Interface Controller The ATA Interface Controller portion of the ASIC provides data handling bus control and transfer management servic...

Page 54: ...le filter for partial response signal conditioning 5 2 2 5 5 2 2 5 5 2 2 5 5 2 2 5 Flash A D Converter Flash A D Converter Flash A D Converter Flash A D Converter Provides very high speed digitization of the processed read signal 5 2 2 6 5 2 2 6 5 2 2 6 5 2 2 6 Viterbi Detector Viterbi Detector Viterbi Detector Viterbi Detector Decodes ADC result into binary bit stream 5 2 2 7 5 2 2 7 5 2 2 7 5 2 ...

Page 55: ...5 3 1 1 5 3 1 1 5 3 1 1 Adaptive Caching Adaptive Caching Adaptive Caching Adaptive Caching The cache buffer for the Quantum Fireball Plus AS drives features adaptive segmentation for more efficient use of the buffer s RAM With this feature the buffer space used for read and write operations is dynamically allocated The cache can be flexibly divided into several segments under program control Each...

Page 56: ...ther than as individual blocks of data separated by disk access delays This is achieved by taking advantage of the ability to write blocks of data sequentially on a disk that is formatted with a 1 1 interleave This means that as the last byte of data is transferred out of the write cache and the head passes over the next sector of the disk the first byte of the of the next block of data is ready t...

Page 57: ...g is also used to minimize the latency time associated with a single cylinder seek The next logical sector of data that crosses a cylinder boundary is positioned on the drive such that after a single cylinder seek is performed and when the drive is ready to continue accessing data the sector to be accessed is positioned directly under the read write head Therefore the cylinder skew takes place bet...

Page 58: ...rror correction techniques to reduce the uncorrectable read block error rate to less than one bit in 1 x 1014 bits read When errors occur an automatic retry of 15 10 bit symbols and a more rigorous 16 10 bit symbols correction algorithm enable the correction of any sector with single bursts or up to sixteen multiple random one 10 bit symbol burst In addition to these advanced error correction capa...

Page 59: ...be corrected Each time a sector of data is read the Quantum Fireball Plus AS drives will generate a new set of ECC check symbols and cross checking bytes from the user data These new check symbols are compared to the ones originally written to the disk The difference between the newly computed and original check symbols is reflected in a set of 32 syndromes and three cross checking syndromes which...

Page 60: ...fect Management In the factory the media is scanned for defects If a sector on a cylinder is found to be defective the address of the sector is added to the drive s defect list Sectors located physically subsequent to the defective sector are assigned logical block addresses such that a sequential ordering of logical blocks is maintained This inline sparing technique is employed in an attempt to e...

Page 61: ...Basic Principles of Operation Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT 5 16 ...

Page 62: ...Basic Principles of Operation 5 17 Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT ...

Page 63: ...e BIOS communicates directly with the drive s built in controller It issues commands to the drive and receives status information from the drive 6 3 6 3 6 3 6 3 MECHANICAL DESCRIPTION MECHANICAL DESCRIPTION MECHANICAL DESCRIPTION MECHANICAL DESCRIPTION 6 3 1 6 3 1 6 3 1 6 3 1 Drive Cable and Connector Drive Cable and Connector Drive Cable and Connector Drive Cable and Connector The hard disk drive...

Page 64: ... C The drive does not use all of the signals provided by the ATA bus Table 6 4 shows the relationship between the drive connector J1 section C and the ATA bus Note Note Note Note In Table 6 1 the following conventions apply A minus sign follows the name of any signal that is asserted as active low Direction DIR is in reference to the drive IN indicates input to the drive OUT indicates output from ...

Page 65: ... data transfers from the host data bus DD0 DD7 or DD0 DD15 to a register or to the drive s data port Ground Ground 24 Ground between the host system and the drive I O Read DIOR IN 25 The rising edge of this read strobe provides a clock for data transfers from a register or the drive s data port to the host data bus DD0 DD7 or DD0 DD15 The rising edge of DIOR latches data at the host Ground Ground ...

Page 66: ...he Device Control Register or when the host writes to the Command Register or reads the Status Register When data is being transferred in programmed I O PIO mode INTRQ is asserted at the beginning of each data block transfer Exception INTRQ is not asserted at the beginning of the first data block transfer that occurs when any of the following commands executes FORMAT TRACK Write Sector WRITE BUFFE...

Page 67: ...and has not yet passed its internal diagnostics If drive 1 is present drive 0 waits for drive 1 to assert PDIAG for up to 5 seconds after the receipt of a valid EXECUTE DRIVE DIAGNOSTIC command Since PDIAG indicates that drive 1 has passed its internal diagnostics and is ready to provide status drive 1 clears BSY prior to asserting PDIAG If drive 1 fails to respond during reset initialization driv...

Page 68: ...nal DASP is deasserted following the receipt of a valid command by drive 1 or after the drive is ready whichever occurs first Once DASP is deasserted either hard drive can assert DASP to light the drive activity LED Each drive has a 10K pull up resistor on this signal If an external drive activity LED is used to monitor this signal an external resistor must be connected in series between the signa...

Page 69: ...able detection Device Based Cable detection Device Based Cable detection Following the issuing of an ID command by the host the device will respond by Asserts PDIAG CBLID drives it low for 30 ms minimum Releases PDIAG CBLID Measures level of PDIAG CBLID 2 to 13 ms after releasing it The detected electrical level of PDIAG CBLID will be stored in ID word 93 bit 13 refer to Table 6 24 PDIAG CBLID les...

Page 70: ...ds IORDY on READ commands STOP DIOW CBLID PDIAG J1 PIN J1 PIN J1 PIN J1 PIN NUMBER NUMBER NUMBER NUMBER DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION HOST HOST HOST HOST DIR DIR DIR DIR DEV DEV DEV DEV ACRONYM ACRONYM ACRONYM ACRONYM 28 CABLE SELECT CSEL 37 CHIP SELECT 0 CS0 38 CHIP SELECT 1 CS1 17 DATA BUS BIT 0 DD0 15 DATA BUS BIT 1 DD1 13 DATA BUS BIT 2 DD2 11 DATA BUS BIT 3 DD3 9 DATA BUS BI...

Page 71: ...e The PIO host interface timing shown in Table 6 5 is in reference to signals at 0 8 volts and 2 0 volts All times are in nanoseconds unless otherwise noted Figure 6 1 provides a timing diagram 33 DEVICE ADDRESS BIT 1 DA1 36 DEVICE ADDRESS BIT 2 DA2 29 DMA ACKNOWLEDGE DMACK 21 DMA REQUEST DMARQ 31 INTERRUPT REQUEST INTRQ 25 I O READ DMA ready on data in bursts see note 2 Data strobe on data out bu...

Page 72: ... Fireball Plus Fireball Plus AS AS AS AS AT AT AT AT t0 t0 t0 t0 Cycle Time Cycle Time Cycle Time Cycle Time min min min min 120 120 120 120 120 120 120 120 t1 Address Valid to DIOW DIOR Setup min 25 25 t2 DIOW DIOR Pulsewidth 8 or 16 bit min 70 70 t2i DIOW DIOR Negated Pulsewidth min 25 25 t3 DIOW Data Setup min 20 20 t4 DIOW Data Hold min 10 10 t5 DIOR Data Setup min 20 20 t5a DIOR to Data Valid...

Page 73: ...MIN MAX MIN MAX MODE 2 MODE 2 MODE 2 MODE 21 1 1 1 local bus local bus local bus local bus 1 ATA Mode 2 timing is listed for reference only Quantum Quantum Quantum Quantum Fireball Plus Fireball Plus Fireball Plus Fireball Plus AS AS AS AS AT AT AT AT t0 t0 t0 t0 Cycle Time Cycle Time Cycle Time Cycle Time min min min min 120 120 tD DIOR DIOW Pulsewidth min 70 70 tE DIOR to Data Valid max tF DIOR ...

Page 74: ...x Max Min Min Min Min Max Max Max Max Min Min Min Min Max Max Max Max Min Min Min Min Max Max Max Max Min Min Min Min Max Max Max Max t2CYCTYP 240 160 120 90 60 40 Sender tCYC 112 73 54 39 25 16 8 Recipient t2CYC 230 153 115 86 57 38 Sender tDS 15 0 10 0 7 0 7 0 5 0 4 0 Recipient tDH 5 0 5 0 5 0 5 0 5 0 4 6 Recipient tDVS 70 0 48 0 31 0 20 0 6 7 4 8 Sender tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Sender tCS 1...

Page 75: ...t from STROBE edge until data may become invalid see note 2 5 tDVS Data valid setup time at sender from data valid until STROBE edge see note 3 tDVH Data valid hold time at sender from STROBE edge until data may become invalid see note 3 tCS CRC word setup time at device see note 2 tCH CRC word hold time device see note 2 tCVS CRC word valid setup time at host from CRC valid until DMACK negation s...

Page 76: ... be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull up on IORDY giving it a known state when released 5 ...

Page 77: ...e host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until well after they are driven by the device DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 Tzad DA0 DA1 DA2 CS0 CS1 Tui Tzad Tack Tack Tenv Tenv Tziordy Tfs Tfs Tdvs Taz Tdvh Tack Tdvh DSTROBE at device DD 15 0...

Page 78: ...HDMARDY is negated and may then assert STOP to terminate the burst Tsr timing need not be met for an asynchronous pause Figure 6 6 Figure 6 6 Figure 6 6 Figure 6 6 Device Terminating a Data In Burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device Tsr Trfs Trp Taz Tiordyz CRC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 Tack ...

Page 79: ...gure 6 8 Figure 6 8 Figure 6 8 Figure 6 8 Initiating a Data Out Burst Tdvh CRC Taz DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 Tack Tmli Tli Tli Tiordyz Tack Tack Tzah Tmli Tdvs Trfs Trp DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 Tui Tack Tenv Tziordy Tli Tdvs Tdvh Tack Tack Tui ...

Page 80: ...idered stable at the device until well after they are driven by the host Figure 6 10 Figure 6 10 Figure 6 10 Figure 6 10 Device Pausing a Data Out Burst Note Note Note Note The device knows the burst is fully paused Trp ns after DDMARDY is negated and may then negate DMARQ to terminate the burst Tsr timing need not be met for an asynchronous pause Tdh Tds Tdvh HSTROBE at host DD 15 0 at host HSTRO...

Page 81: ... 20 5 30 0 40 0 60 0 GB AT 6 19 Figure 6 11 Figure 6 11 Figure 6 11 Figure 6 11 Host Terminating a Data Out Burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 Tack Tli Tmli Tdvs Tli Tli Tack Tiordyz Tack CRC Tdvh Tss ...

Page 82: ...ace RESET timing shown in Table 6 9 is in reference to signals at 0 8 volts and 2 0 volts All times are in nanoseconds unless otherwise noted Figure 6 13 provides a timing diagram Table 6 9 Table 6 9 Table 6 9 Table 6 9 Host Interface RESET Timing Figure 6 13 Figure 6 13 Figure 6 13 Figure 6 13 Host Interface RESET Timing SYMBOL DESCRIPTION MINIMUM MAXIMUM tM RESET Pulse width 25 DMARQ device DMAC...

Page 83: ...egisters when transmitting control like a software reset Table 6 10 lists the selection addresses for these registers Table 6 10 Table 6 10 Table 6 10 Table 6 10 I O Port Functions and Selection Addresses FUNCTION FUNCTION FUNCTION FUNCTION HOST SIGNALS HOST SIGNALS HOST SIGNALS HOST SIGNALS CONTROL BLOCK REGISTERS CONTROL BLOCK REGISTERS CONTROL BLOCK REGISTERS CONTROL BLOCK REGISTERS CS1FX CS1FX...

Page 84: ...nate Status Register Alternate Status Register Alternate Status Register The Alternate Status Register contains the same information as the Status Register in the command block Reading the Alternate Status Register does not imply the acknowledgment of an interrupt by the host or clear a pending interrupt See the description of the Status Register in section 6 6 2 8 for definitions of bits in this ...

Page 85: ...CRIPTION 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 1 Always 1 2 SRST1 1 SRST Host Software Reset bit When the host sets this bit the drive is reset When two drives are daisy chained on the interface this bit resets both drives simultaneously Host software reset bit 1 nIEN2 2 nIEN Drive Interrupt Enable bit When nIEN equals 0 or the host has selected the drive the drive enables the host interru...

Page 86: ...ster contains status information about the last command executed by the drive The contents of this register are valid only when the Error bit ERR in the Status Register is set to 1 The contents of the Error Register are also valid at power on and at the completion of the drive s internal diagnostics when the register contains a status code When the error bit in the Status Register is set to 1 the ...

Page 87: ...first sector to be accessed by a subsequent command The sector number is a value between one and the maximum number of sectors per track As the drive transfers each sector it increments the Sector Number Register See the command descriptions in section 6 7 for information about the contents of the Sector Number Register after successful or unsuccessful command completion In LBA mode this register ...

Page 88: ...ws the Drive Head Register bits Table 6 15 Table 6 15 Table 6 15 Table 6 15 Drive Head Register Bits MNEMONIC MNEMONIC MNEMONIC MNEMONIC BIT BIT BIT BIT DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Reserved 71 1 Bits 5 7 define the sector size set in hardware 512 bytes Always 1 L 62 2 Bit 6 is the binary encoded Address Mode Select When bit 6 is set to 0 addressing is by CHS mode When bit 6 is ...

Page 89: ...owing conditions Within 400 ns after the deassertion of RESET or after SRST is set in the Device Control Register Following a reset BSY will be set for no longer than 30 seconds Within 400 ns of a host write to the Command Block Registers with a Read READ LONG READ BUFFER SEEK RECALIBRATE INITIALIZE DRIVE PARAMETERS Read Verify Identify Drive or EXECUTE DRIVE DIAGNOSTIC command Within 5 µsec after...

Page 90: ... COMMAND COMMAND PARAMETER PARAMETER PARAMETER PARAMETER NAME NAME NAME NAME CODE CODE CODE CODE SC SC SC SC Ex Ex Ex Ex Sub Sub Sub Sub Code Code Code Code SN SN SN SN CY CY CY CY DS DS DS DS HD HD HD HD FR FR FR FR RECALIBRATE 1Xh V READ SECTORS 20h V V V V V WRITE SECTORS 30h V V V V V READ VERIFY SECTORS 40h V V V V V SEEK 7Xh V V V V EXECUTE DRIVE DIAGNOSTIC 90h INITIALIZE DRIVE PARAMETERS 91...

Page 91: ...o longer busy BSY 0 2 Activate the Interrupt Enable IEN bit 3 Wait for the drive to set RDY RDY 1 4 Load the required parameters into the Command Block Register 5 Write the command code to the Command Register Execution of the command begins as soon as the drive loads the Command Block Register The remainder of this section describes the function of each command The commands are listed in the same...

Page 92: ... 2 1 1 1 1 0 0 0 0 Error na na na na na ABRT TK0NF na Sector Count na Sector Number na Cylinder Low na Cylinder High Device Head obs na obs DEV HEAD number or LBA Status BSY DRDY na na DRQ na na ERR Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector count or LBA Cylinder Low Cylinder low or ...

Page 93: ...an interrupt to start the first buffer fill operation Once the buffer is full the drive clears DRQ sets BSY and begins execution of the command INPUTS ERROR OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector count or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or...

Page 94: ...ter Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device Head obs LBA obs DEV na Head Number or LBA Command 40h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na UN...

Page 95: ... accept and queue subsequent commands while performing the seek If the Cylinder registers contain an illegal cylinder the drive sets the ERR bit in the Status Register and the IDNF bit in the Error Register INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector Number or LBA Cylin...

Page 96: ...ive 0 appends 80h with its own diagnostics status If the host detects a drive 1 diagnostic failure when reading drive 0 status it sets the DRV bit then reads the drive 1 status If drive 1 is not present Drive 0 reports only its own diagnostic results Drives 0 clears BSY and generates an interrupt The diagnostic code written to the error is a unique 8 bit code Table 6 18 list the diagnostics codes ...

Page 97: ...count Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device Head obs LBA obs DEV na Head Number or LBA Command 90h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error Diagnostic Code Sector Count Signature Sector Number Signature Cylinder Low Signature Cylinder High Signature Device Head S...

Page 98: ...e Head register which specifies the number of heads minus 1 The DRV bit assigns these values to drive 0 or drive 1 This command does not check the sector count and head values for validity If these values are invalid the drive will not report an error until another command causes an illegal access INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 ...

Page 99: ...WNLOAD MICROCODE command is vendor specific All transfers will be an integer multiple of the sector size The size of the data transfer is determined by the contents of the Sector Number register and the Sector Count register The Sector Number register will be used to extend the Sector Count register to create a sixteen bit sector count value The Sector Number register will be the most significant ...

Page 100: ...plemented this command shall be implemented PROTOCOL Non data command INPUTS The Features register shall be set to D9h The Cylinder Low register shall be set to 4Fh The Cylinder High register shall be set to C2h NORMAL OUTPUTS None ERROR OUTPUTS If the device does not support this command if SMART is not enabled or if the values in the Features Cylinder Low or Cylinder High registers are invalid a...

Page 101: ...ENABLE OPERATIONS are disabled and invalid and shall be aborted by the device including SMART DISABLE OPERATIONS commands returning the Aborted command error 6 7 9 1 6 7 9 1 6 7 9 1 6 7 9 1 SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE COMMAND CODE B0h TYPE Optional SMART Feature set I...

Page 102: ...power off sequence or during an error recovery sequence A value of F1h written by the host into the device s Sector Count register before issuing this command will cause this feature to be enabled Any other meaning of this value or any other non zero value written by the host into this register before issuing this command is vendor specific The meaning of any non zero value written to this registe...

Page 103: ... enables access to all SMART capabilities within the device Prior to receipt of this command attribute values are neither monitored nor saved by the device The state of SMART either enabled or disabled will be preserved by the device across power cycles Once enabled the receipt of subsequent SMART ENABLE OPERATIONS commands shall not affect any of the attribute values Upon receipt of this command ...

Page 104: ... the host Upon receipt of this command from the host the device sets BSY reads the attribute thresholds from non volatile memory sets DRQ clears BSY asserts INTRQ and then waits for the host to transfer the 512 bytes of attribute threshold information from the device via the Data register The following defines the 512 bytes that make up the attribute threshold information The sequence of active at...

Page 105: ...olds Data Structure Table 6 20 Table 6 20 Table 6 20 Table 6 20 Individual Threshold Data Structure Description Description Description Description Bytes Bytes Bytes Bytes Format Format Format Format Type Type Type Type Data structure revision number 0x0004h for this revision 2 binary Rd only 1st attribute threshold 12 Rd only 30th attribute threshold 12 Rd only reserved 0x00 18 Rd only Vendor spe...

Page 106: ... attribute values is described in Table 6 21 Prior to the monitoring and saving of attribute values all values are set to 0x64h The attribute values of 0x00h and 0xFFh are reserved and should not be used by the device SMART capability SMART capability SMART capability SMART capability Bit 0 Pre power mode attribute saving capability If the value of this bit equals one the device will save its attr...

Page 107: ...OR OUTPUTS If the device does not support this command if SMART is disabled or if the values in the Features Cylinder Low or Cylinder High registers are invalid an Aborted command error is posted PREREQUISITES DRDY set equal to one SMART enabled DESCRIPTION This command is used to communicate the reliability status of the device to the host at the host s request Upon receipt of this command the de...

Page 108: ...sters are invalid an Aborted command error is posted PREREQUISITES DRDY set equal to one SMART enabled DESCRIPTION This command causes the device to immediately save any updated attribute values to the device s non volatile memory regardless of the state of the attribute autosave timer Upon receipt of this command from the host the device sets BSY writes any updated attribute values to non volatil...

Page 109: ...TS If the device does not support this command if SMART is disabled or if the values in the Features Cylinder Low or Cylinder High registers are invalid an Aborted command error is posted Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features D4h Sector Count na Sector Number na Cylinder Low 4Fh Cylinder High C2h Device Head obs ns obs DEV na n...

Page 110: ...required at the start of the data block The data block length in sectors is defined in the SET MULTIPLE command READ MULTIPLE is only valid when the READ MULTIPLE commands are enabled INPUTS Value Value Value Value Definition Definition Definition Definition 00h or 80h Off line data collection was never started 02h or 82h Off line data collection was completed without error 04h or 84h Off line dat...

Page 111: ... 1 1 1 1 0 0 0 0 Error na unc na IDNF na ABRT na obs Sector Count na Sector Number Sector Number or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device Head obs Na obs DEV HEAD number or LBA Status BSY DRDY DF na DRQ na na ERR Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector N...

Page 112: ...uses an Aborted Command error and disables execution of READ MULTIPLE and WRITE MULTIPLE commands If the Sector Count Register contains a zero value when the host issues the command READ MULTIPLE and WRITE MULTIPLE commands are disabled Any unsupported block count in the register causes an aborted command error and disables READ MULTIPLE and WRITE MULTIPLE commands After the command is executed th...

Page 113: ... 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector count or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device Head obs LBA obs DEV na Head Number or LBA Command C8h C9 Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error icrc unc na IDNF na ABRT na na Sector Count na Sector Number...

Page 114: ...gister Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Sector count Sector Number Sector count or LBA Cylinder Low Cylinder low or LBA Cylinder High Cylinder high or LBA Device Head obs LBA obs DEV na Head Number or LBA Command CAh Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error ICRC na na I...

Page 115: ...ng area This is the default setting Three commands are available which are not dependent upon the APD counter reaching zero Sleep When a sleep command is received the drive enters the sleep mode In the sleep mode the spindle and actuator motors are off and the heads are latched in the landing zone Receipt of a reset causes the drive to transition from the sleep to the standby mode Standby Immediat...

Page 116: ...tor the drive s PCB power is on and the heads are parked INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na obs na obs DEV na na na na E0h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na na na na na ABRT n...

Page 117: ...UTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E1h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na na na na na ABRT na na Sector Count na Sector Number na Cylinder Lo...

Page 118: ...5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Time Period Value Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E2h Sector Count Value Sector Count Value Sector Count Value Sector Count Value TIME TIME TIME TIME 0 Timer Disabled 1 to 12 1 minute 13 to 240 value 5 seconds 241 to 251 Value 240 30 minutes 252 to 255 Value 5 minutes Register...

Page 119: ... accessed the countdown timer is reset to the value originally set in the Sector Count register at the time the IDLE mode auto power down command was issued INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count Time Period Value Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Comma...

Page 120: ...RQ clears BSY and generates an interrupt The host then reads up to 512 bytes of data from the buffer INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E4h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 ...

Page 121: ... 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E5h Sector Count Result Value Sector Count Result Value Sector Count Result Value Sector Count Result Value Status Status Status Status 00h Standby Mode 80h Idle Mode FFh Active mode or Idle mode Register Register Regis...

Page 122: ...red before issuing any command to the drive INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E6h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na na na na na ...

Page 123: ...ds to write all the cached data to the media INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E7h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na na na na na...

Page 124: ...rs BSY and generates an interrupt The host then writes up to 512 bytes of data to the buffer INPUTS OUTPUTS Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command E8h Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 ...

Page 125: ...umber of Unformatted Bytes Per Track The number of unformatted bytes per translated track in the default translation mode Number of Unformatted Bytes Per Sector The number of unformatted bytes per sector in the default translation mode Number of Logical Sectors Per Track The number of sectors per track in the default translation mode Serial Number The contents of this field are left aligned and pa...

Page 126: ...1 0 0 0 0 Features na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na Command ECh Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Error na na na na na ABRT na na Sector Count na Sector Number na Cylinder Low na Cylinder High na Device Head obs na obs DEV na na na na Status BSY DRDY DF na DRQ na na E...

Page 127: ... below are true if the bit is set to 1 WORD WORD WORD WORD BIT BIT BIT BIT BIT BIT BIT BIT VALUE VALUE VALUE VALUE 0 15 0 0 ATA device 14 0 Retired 13 0 12 0 11 0 10 1 9 0 8 0 7 0 1 Removable media 6 1 1 Not removable controller and or device 5 0 Retired 4 1 3 1 2 0 1 1 0 0 Reserved 1 10 2AT 16 383 20 5AT 16 383 30 0AT 16 383 40 0AT 16 383 60 0AT 16 383 Default logical cylinders 2 0 Reserved 3 10 ...

Page 128: ...Capabilities 51 15 8 7 0 4 0 PIO data transfer cycle timing mode Vendor Unique 52 15 8 7 0 N A Retired 53 15 3 2 1 0 1 1 1 Reserved The fields reported in word 88 are valid The fields reported in words 64 70 are valid The fields reported in words 54 58 are valid 54 Number of current cylinders 55 Number of current heads 56 X Number of current sectors per track 57 58 X Current capacity in sectors CH...

Page 129: ...version number 0000h or FFFFh device does not report version 82 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 306Bh Command set supported If words 82 and 83 0000h or FFFFh command set notification not supported Obsolete 1 NOP command supported 1 READ BUFFER command supported 1 WRITE BUFFER command supported Obsolete 1 Host Protected Area feature set supported 1 DEVICE RESET command supported 1 SERVICE int...

Page 130: ...s not supported Will be cleared to zero Will be set to one Reserved 85 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3069h Command set feature enabled If words 85 86 and 87 0000h or FFFFh command set enabled notification is not supported Obsolete 1 NOP command supported 1 READ BUFFER command supported 1 WRITE BUFFER command supported Obsolete 1 Host Protected Area feature set supported 1 DEVICE RESET comm...

Page 131: ...ra DMA mode 4 is active Ultra DMA mode 4 is not active Ultra DMA mode 3 is active Ultra DMA mode 3 is not active Ultra DMA mode 2 is active Ultra DMA mode 2 is not active Ultra DMA mode 1 is active Ultra DMA mode 1 is not active Ultra DMA mode 0 is active Ultra DMA mode 0 is not active Reserved Ultra DMA mode 5 and below are supported Ultra DMA mode 4 and below are supported Ultra DMA mode 3 and b...

Page 132: ...MTCYJJJLSSSSBBB where 00 Placeholders QT Quantum M Place of manufacture T Drive type family fixed at 2 C Drive capacity Y Last digit of year drive built JJJ Julian date L Manufacturing production line SSSS Sequence of manufacture BBB Blanks placeholders 3 n is a variable from zero to 16 4 Model Numbers are byte swapped for readability See Note 1 ...

Page 133: ... can choose the transfer mechanism by Set Transfer Mode and specifying a value in the Sector Count register The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value 6 7 26 6 7 26 6 7 26 6 7 26 Set Features Ultra ATA 100 Set Features Ultra ATA 100 Set Features Ultra ATA 100 Set Features Ultra ATA 100 Set Transfer Mode Set Transfer Mode Set Transfer Mode Set Transf...

Page 134: ...AL COMMAND if the bytes are not entered correctly The AT Read Defect List command is an extended AT command that enables the host to retrieve the drive s defect list The host begins by writing to address 1F6h to select the drive Then the host writes to addresses 1F2h 1F5h using values indicated in Table 6 27 When the host subsequently writes the extended command code F0h to address 1F7h the drive ...

Page 135: ...es are not entered correctly Pending defects will be excluded from the list since no alternate sector is being used as their replacement and since they may be removed from the drive s internal pending list at a later time Table 6 28 shows the overall format of the defect list and Table 6 29 shows the format of the individual defect entries ADDRESS ADDRESS ADDRESS ADDRESS VALUE VALUE VALUE VALUE DE...

Page 136: ...ote Note Bytes 4 7 will be set to FFh for bad track entries BYTE BYTE BYTE BYTE DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0 0 1 1Dh 2 8 Number of Defects MSB 3 8 Number of Defects LSB 4 11 Defect Entry 1 12 19 Defect Entry 2 BYTE BYTE BYTE BYTE DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0 Defect cylinder MSB 1 Defect cylinder 2 Defect cylinder LSB 3 Defect head 4 Defect sector MSB 5 Def...

Page 137: ...k Registers The first byte 01h is a subcode to the extended command code F0h Table 6 30 Table 6 30 Table 6 30 Table 6 30 Accessing the READ CONFIGURATION Command Note Note Note Note In Table 6 30 Only the value in address 1F2h of the Command Block Registers is different from the SET CONFIGURATION command Registers 1F2h through 1F5h must contain the exact values shown in Table 6 30 These values fun...

Page 138: ...ONFIGURATION Command Note Note Note Note Registers 1F2h through 1F5h must contain the exact values shown above These values function as a key The drive issues the message ILLEGAL COMMAND if the key is not entered correctly To select the drive being reconfigured register 1F6h should be set For execution of the command to begin load register 1F7h with F0h 6 7 28 3 6 7 28 3 6 7 28 3 6 7 28 3 Set Conf...

Page 139: ...Command Data Field Configuration Command Data Field A 512 byte data field is associated with this command This data field is sent to the drive through a normal 512 byte write handshake Table 6 33 shows the format of the data field Bytes 0 through 31 of the data field contain additional KEY information The drive issues the message ILLEGAL COMMAND if this information is not entered correctly Bytes 3...

Page 140: ...as a transfer buffer The default setting is 1 6 7 28 7 6 7 28 7 6 7 28 7 6 7 28 7 Error Recovery Parameters Error Recovery Parameters Error Recovery Parameters Error Recovery Parameters AWRE Automatic Write Reallocation Enabled Byte 36 Bit 7 When set to 1 indicates that the drive will enable automatic reallocation of bad blocks Automatic Write Reallocation is similar to the function of Automatic R...

Page 141: ...ting is 0 The drive will post all errors whether DCR is set to 0 or 1 NUMBER OF RETRIES Byte 37 This byte specifies the number of times that the drive will attempt to recover from data errors by rereading the data before it will apply correction The drive performs rereads before ECC correction unless EEC byte 36 bit 3 is set to 1 enabling early correction The default is eight ECC CORRECTION SPAN B...

Page 142: ...ne the maximum address shall be reported as an LBA value If LBA is cleared to 0 the maximum address shall be reported as a CHS value 6 7 29 2 6 7 29 2 6 7 29 2 6 7 29 2 SET MAX SET MAX SET MAX SET MAX Individual SET MAX commands are identified by the value placed in the Features register The following Table shows these Features register values Register Register Register Register 7 7 7 7 6 6 6 6 5 ...

Page 143: ... value DEV will indicate the selected device Bits 3 0 contain the native maximum address head number IDENTIFY DEVICE word 3 minus one or LBA bits 27 24 value to be set Normal Outputs Normal Outputs Normal Outputs Normal Outputs Sector Number Maximum native sector number or LBA bits 7 0 set on the device Cylinder Low Maximum cylinder number low or LBA bits 15 8 set on the device Register Register R...

Page 144: ...MAX ADDRESS command using a new maximum LBA address the content of all IDENTIFY DEVICE words will comply with the following The content of words 61 60 will be equal to the new Maximum LBA address 1 If the content of words 61 60 is greater than 16 514 064 and if the device does not support CHS addressing then the content of words 1 3 6 54 55 56 and 58 57 will equal zero The content of words 3 6 55 ...

Page 145: ...tent of the Features register equal to 02h Inputs Inputs Inputs Inputs Description Description Description Description The SET MAX LOCK command sets the device into Set_Max_Locked state After this command is completed any other Set Max commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected The device remains in this state until a power cycle or the acceptance of a SET MAX UNLOCK or SE...

Page 146: ...device returns command aborted and decrements the unlock counter On the acceptance of the SET MAX LOCK command this counter is set to a value of five and will be decremented for each password mismatch when SET MAX UNLOCK is issued and the device is locked When this counter reaches zero then the SET MAX UNLOCK command will return command aborted until a power cycle If the password compare matches t...

Page 147: ...Description Description Description Description The SET MAX FREEZE LOCK command sets the device to Set_Max_Frozen state After command completion any subsequent SET MAX commands are rejected Commands disabled by SET MAX FREEZE LOCK are SET MAX ADDRESS SET MAX PASSWORD SET MAX LOCK SET MAX UNLOCK Register Register Register Register 7 7 7 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Feat...

Page 148: ...OR REGISTER ERROR REGISTER ERROR REGISTER ERROR REGISTER STATUS REGISTER STATUS REGISTER STATUS REGISTER STATUS REGISTER BBK BBK BBK BBK UNC UNC UNC UNC IDNF IDNF IDNF IDNF ABRT ABRT ABRT ABRT TKO TKO TKO TKO AMNF AMNF AMNF AMNF DRDY DRDY DRDY DRDY DF DF DF DF DSC DSC DSC DSC CORR CORR CORR CORR ERR ERR ERR ERR Check Power Check Power Check Power Check Power Mode Mode Mode Mode V V V V V Execute D...

Page 149: ...all Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT 6 87 DRDY Drive ready DSC Disk seek complete not detected DF Device fault detected ERR Error bit in the Status Register IDNF Requested ID not found TK0 Track zero not found error UNC Uncorrectable data error ...

Page 150: ...ATA Bus Interface and ATA Commands 6 88 Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT ...

Page 151: ... the heads in the landing zone A park utility is not required to park the heads on drives equipped with AIRLOCK all Quantum drives ALLOCATION The process of assigning particular areas of the disk to particular files See also allocation unit ALLOCATION UNIT An allocation unit also known as a cluster is a group of sectors on the disk that can be reserved for the use of a particular file AVERAGE SEEK...

Page 152: ...use by the disk drive CONTROLLER CARD An adapter holding the control electronics for one or more hard disks usually installed in a slot in the computer CPU Acronym for Central Processing Unit The microprocessor chip that performs the bulk of data processing in a computer CRC Acronym for Cyclic Redundancy Check An error detection code that is recorded within each sector and is used to see whether p...

Page 153: ...table stored on the outer edge of a disk that tells the operating system which sectors are allocated to each file and in what order FCI Acronym for flux changes per inch See also BPI FILE SERVER A computer that provides network stations with controlled access to shareable resources The network operating system is loaded on the file server and most shareable devices disk subsystems printers are att...

Page 154: ...y the outer track track 0 HOST ADAPTER A plug in board that forms the interface between a particular type of computer system bus and the disk drive I I I I INITIALIZE See low level formatting INITIATOR A SCSI device that requests another SCSI device to perform an operation A common example of this is a system requesting data from a drive The system is the initiator and the drive is the target INTE...

Page 155: ...Quantum drives are shipped with the low level formatting already done LOW PROFILE Describes drives built to the 3 1 2 inch form factor which are only 1 inch high M M M M MB See megabyte MEDIA The magnetic film that is deposited or coated on an aluminum substrate which is very flat and in the shape of a disk The media is overcoated with a lubricant to prevent damage to the heads or media during hea...

Page 156: ...rage surfaces in a small package The platter is coated with a magnetic material that is used to store data as transitions of magnetic polarity POH Acronym for power on hours The unit of measurement for Mean Time Between Failure as expressed in the number of hours that power is applied to the device regardless of the amount of actual data transfer usage See MTBF POSITIONER See actuator R R R R RAM ...

Page 157: ...itten on the media that guide the read write heads to the proper position SERVO SURFACE A separate surface containing only positioning and disk timing information but no data SETTLE TIME The interval between when a track to track movement of the head stops and when the residual vibration and movement dies down to a level sufficient for reliable reading or writing SHOCK RATING A rating expressed in...

Page 158: ...tions and timing information After formatting user data can be stored on the remaining disk space known as formatted capacity The size of a Quantum drive is expressed in formatted capacity V V V V VOICE COIL A type of motor used to move the disk read write head in and out to the right track Voice coil actuators work like loudspeakers with the force of a magnetic coil causing a proportionate moveme...

Page 159: ...ister 6 28 command register 6 28 Configuration 6 75 configuration command data field 6 77 connector IDE 3 12 control block registers 6 22 cooling fan requirements 3 11 crash stops 5 4 cross checking XC 5 13 cylinder high register 6 26 cylinder low register 6 25 D daisy chain 2 6 daisy chained 3 5 data port register 6 24 data request bit 6 27 Data Synchronizer 5 9 Data transfer operations 5 8 DATA ...

Page 160: ...ations 3 5 jumper locations 3 4 jumper options 3 5 L landing zone 5 4 logical cylinders 3 17 logical heads 3 17 logical sectors track 3 17 low 4 3 low level format 4 3 M maximum screw torque 3 10 mechanical dimensions 3 1 microcontroller 5 7 motherboard 3 13 Motor Controller 5 8 mounting 3 9 mounting dimensions 3 9 mounting holes 3 9 mounting screw clearance 3 10 mounting screws 3 10 MS DOS 3 18 M...

Page 161: ...nfiguration 6 76 set configuration without saving to disk 6 76 set features 6 71 shipping container 3 2 SHOCK 4 9 Slave Present 3 6 slave present SP jumper 3 6 Specifications 4 9 sputtered thin film coating 5 3 status register 6 27 busy bit 6 27 data request bit 6 27 drive ready bit 6 27 drive write fault bit 6 27 error bit 6 27 status register bits 6 27 supply voltages 4 4 syndrome values 5 14 T ...

Page 162: ...Index I 4 Quantum Fireball Plus AS 10 2 20 5 30 0 40 0 60 0 GB AT ...

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