Quantum Design Advance 6E, Manual

Page: 30 / 64

Manual for Advance 6E series
Advanced Chipset Features Setup
Figure-4 Advanced Chipset Features Setup Menu
The following indicates the options for each item and describes their meaning.
Item Option Description
l Close Empty Enabled Closes empty DIMM or PCI clock to reduce
DIMM/PCI Clk EMI.
Disabled Does not close empty DIMM or PCI clock.
l Bank 0/1, 2/3, 4/5 SDRAM 8/10ns These items are of selected DRAM read/write
DRAM Timing Normal timing. Default setting is recommended.
Medium
Fast
Turbo
l SDRAM Cycle 2/3 Defines the CLT timing parameter of SDRAM
Length Auto expressed in 66MHz clocks.
Latency Time = 2 clocks
Latency Time = 3 clocks
l DRAM Clock Host Clk DRAM clock is same as host clock.
Hclk+33M DRAM clock is faster than host clock by 33MHz.
Hclk-33M DRAM clock is slower than host clock by 33MHz.
Note: the system will display different choices
according to the CPU host clock.
l Memory Hole 15M~16M Memory Hole at 15-16M is reserved for expanded
ISA card.
Disabled Does not set this memory hole.
l P2C/C2P Enabled Enables P2C/C2P concurrency.
Concurrency Disabled Disables P2C/C2P concurrency.
l Fast R-W Turn Enabled Enables Fast R-W Turn Around.
Around Disabled Disables Fast R-W Turn Around.
Award BIOS Description