QDI BrillianX 1S/2000, Manual

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Manual BrillianX 1S/2000
Chipset Features Setup
Figure-5 Chipset Features Setup Menu
The following indicates the options for each item and describes their meaning.
Item Option Description
l
SDRAM CAS 2 Defines the CLT timing parameter of SDRAM.
Latency Time Latency Time=2x system clocks.
3 Latency Time=3x system clocks.
l
SDRAM Percharge Enabled Default setting is suggested.
Control
Disabled
l
DRAM ECC Select ECC Provides ECC (Error Checking and Correction)
function.
Non-ECC Disables ECC function.
l
Video BIOS Enabled Beside conventional memory, video BIOS area is
Cacheable also cacheable.
Disabled Video BIOS area is not cacheable.
l
Video RAM Enabled Besides conventional memory, video BIOS area is
Cacheable also cacheable.
Disabled Video BIOS area is not cacheable.
l 8 Bit I/ O Recovery 1~ 8 Defines the ISA Bus 8 bit I/O operating recovery
Time time.
NA 8 bit I/O recovery time does not exist.
l 16 Bit I / O Recovery 1~ 4 Defines the ISA Bus 16 bit I/O operating recovery
Time time.
NA 16 bit I/O recovery time does not exist.
l
Memory hole at
Enabled Memory hole at 15-16M is reserved for expanded
15M-16M
ISA card
Disabled Does not set this memory hole.
36
Award BIOS Description