protech PC-550, User Manual, Page: 69 / 106

Chapter 5 Award BIOS Setup
PC-550 USER
′
S MANUAL
Page: 5-11
5-5 CHIPSET FEATURE SETUP
Choose the
〝
CHIPSET FEATURES SETUP
〞
from the main menu, the
screen shown as below.
ROM PCI/ISA BIOS (2A59FP6C)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration
DRAM Timing
DRAM RAS# Precharge Time
DRAM R/W Leadoff Timing
Fast RAS# To CAS# Delay
DRAM Read Burst (EDO/FPM)
DRAM Write Burst Timing
Turbo Read Leadoff
DRAM Speculative Leadoff
Turn-Around Insertion
ISA Clock
System BIOS Cacheable
Video BIOS Cacheable
8 Bit I/O Recovery Time
: Enable
: 70 ns
: 4
: 7/6
: 3
:
x333/x444
: x333
: Disabled
: Disabled
: Disabled
: PCICLK/4
: Disabled
: Disabled
: 1
Memory Parity / ECC Check
Single Bit Error Report
L2 Cache Cacheable Size
Chipset NA# Asserted
Pipline Cache Timing
Passive Release
Delayed Transaction : Auto
: Enabled
: 64MB
: Enabled
: Faster
: Enabled
: Disabled
16 Bit I/O Recovery Time
Memory Hole At 15M-16M
Peer Concurrency
Chipset Special Features
DRAM ECC/PARITY Select : 1
: Diabled
: Enabled
: Enabled
: Parity
Esc : Quit
↑↓→←
: Select Item
F1 : Help Pu/Pd/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Chipset Features Setup
By moving cursor to the desired selection and pressing < F1 > key, the all
options for the desired selection will be displayed for choice. User has to use
select the desired option.
AUTO CONFIGURATION FUNCTION:
When this option is Enabled, the BIOS automatically configures cache and
clock settings based on detection of the CPU clock speed, you cannot change
the other parameters. Set this option to Disabled to manually set DRAM, cache
and I/O bus clock operating parameters.
DRAM Mode:
The number of wait states added on reads to DRAM. Fewer wait states
improve performance.