Each PPI contains a Control Register. This write-only, 8-bit register is used to set the mode and direction of
the groups. At Power-Up or Reset, all I/O lines are set as inputs. Each PPI should be configured during
initialization by writing to the Control Registers even if the groups are only going to be used as inputs.
Output buffers are automatically set by hardware according to the Control Register states. Note that
Control Registers are located at base a3 and base a7. Bit assignments in each of these
Control Registers are as follows:
Bit
Assignment
Code
D0
Port C Lo (C0-C3)
1=Input, 0=Output
D1
Port B
1=Input, 0=Output
D2
Mode Select
1=Mode 1, 0=Mode 0
D3
Port C Hi (C4-C7)
1=Input, 0=Output
D4
Port A
1=Input, 0=Output
D5,D6
Mode Select
00=Mode 0, 01=Mode 1, 1x=Mode 2
D7
Mode Set Flag
1=Active
Table 6-2:
Control Register Bit Assignment
Note
Mode 1 cannot be used by these cards without modification. Thus, bits D2, D5, and D6 should always be
set to "0". If your card has been modified to operate in Mode 1, then there will be an Addendum page in the
front of this manual. These cards cannot be used in Mode 2 of the PPI.
Note
In Mode 0, do not use the control register byte for the individual bit control feature. The hardware uses the
I/O bits to control buffer direction on this card. The control register should only be used for setting up input
and output of the ports and enabling the buffer.
These cards provide a means to enable/disable the tristate I/O buffers under program control. If the
TST/BEN jumper on the card is installed in the BEN position, the I/O buffers are permanently enabled.
However, if that jumper is in the TST position, enable/disable of the buffers is software controlled via the
control register as follows:
a.
The card is initialized in the receive mode by the computer reset command.
b.
When bit D7 of the Control Register is set high, direction of the three groups of the associated PPI
chip as well as the mode can be set. For example, a write to Base A3 with data bit D7 high
programs port direction at Group 0 ports A, B, and C. If, for example, hex 80 is sent to Base
A3, the Port 0 PPI will be configured in mode 0 with Groups A, B, and C as outputs.
At the same time, data bit D7 is also latched in a buffer controller for the associated PPI chip. A high state disables
the buffers and, thus, all four buffers will be put in the tristate mode; i.e. disabled.
c.
Now, if any of the groups are to be set as outputs, you may set the values to the respective group
with the outputs still in the tristate condition. (If all groups are to be set as inputs, this step is not
necessary.)
d.
If data bit D7 is low when the control byte is written, ONLY the associated buffer controller is
addressed. If, for example, a control byte of hex 80 has been sent as previously described, and the
data to be output are correct, and it is now desired to open the three groups, then it is necessary to
send a control byte of hex 00 to base a3 to enable the port 0 buffers. When you do this,
the buffers will be enabled.
Manual PCI-DIO-48(S)
18
