Point Grey Flea3 GigE Technical Reference
E Control and Status Registers
E.4
GPIO_CTRL_PIN: 1110h-1140h
These registers provide control over the GPIO pins.
Pin
Register
0
GPIO_CTRL_PIN_0
1110h
1
GPIO_CTRL_PIN_1
1120h
2
GPIO_CTRL_PIN_2
1130h
3
GPIO_CTRL_PIN_3
1140h
Field
Bit
Description
Presence_Inq
[0]
Presence of this feature
0: Not Available, 1: Available
[1-11]
Reserved
Pin_Mode
[12-15]
Current GPIO Mode:
0: Input
1: Output
2: Asynchronous Trigger
3: Strobe
4: Pulse width modulation (PWM)
[16-30]
For Modes 0, 1, and 2: Reserved
For Mode 4 (PWM:) see below
Data
[31]
For Modes 0, 1, and 2: Data field
0 = 0 V (falling edge), 1 = +3.3 V (rising edge)
For Mode 4 (PWM): see below
Pwm_Count
[16-23]
Number of PWM pulses
Read: The current count; counts down the remaining pulses. After reaching zero, the count does
not automatically reset to the previously-written value.
Write: Writing the number of pulses starts the PWM. Write 0xFF for infinite pulses. (Requires
write of 0x00 before writing a different value.)
[24]
Reserved
En_Pin
[25-27]
The GPIO pin to be used as a PWM enable i.e. the PWM continues as long as the En_Pin is held
in a certain state (high or low).
[28]
Reserved
Disable_Pol
[29]
Polarity of the PWM enable pin (En_Pin) that will disable the PWM. If this bit is 0, the PWM is
disabled when the PWM enable pin goes low.
En_En
[30]
0: Disable enable pin (En_Pin) functionality
1: Enable En_Pin functionality
Pwm_Pol
[31]
Polarity of the PWM signal
0: Low, 1: High
Format:
Revised 10/29/2013
Copyright ©2010-2013 Point Grey Research Inc.
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