USB3382-AIC RDK
© PLX Technology, www.plxtech.com
Page 18 of 34
06Aug12, version 1.3
continues
to
fail
when
the
LTSSM
is
in
the
Configuration
state,
the
LTSSM
continues
to
alternate
between
Gen
1
and
Gen
2
advertisement
every
time
it
exits
the
Detect
state
H =
The
Data
Rate
Identifier
symbol
in
the
TS
Ordered
‐
Sets
always
advertises
support
for
both
the
5.0
GT/s
(Gen
2)
data
rate
and
Autonomous
Change.
Default Setting = H
Table 5. SW2 Functions
SW2 Functional Description
Switch Position Settings
TESTMODE[3:0]
Factory
Test
only
Default Setting = HLLL
CLKSEL
Selects
between
Onboard
RefClk
and
PCIE
slot
RefClk
L = Onboard RefClk
H = PCIE slot RefClk
Default Setting = H
I
2
CADDR[2:0]
I
2
C Lower Slave Address Bits
Used
to
define
the
default
value
of
the
three
least
significant
bits
of
the
USB
3382
I2C/SMBus
7
‐
bit
Slave
address.
Default Setting = LLL
Table 6. SW3 Functions
SW3 Functional Description
Switch Position Settings
PROBE_MODE#
Factory
Test
Only
Default Setting = H
SERDES_MODE_EN#
Factory
Test
Only
Default Setting = H
PLL_BYPASS#
Factory
Test
Only
Default Setting = H
FAST_BRINGUP#
Factory
Test
Only
Default Setting = H
DEBUG_SEL#
