PLX Technology USB3382-AIC Rapid, Hardware Reference Manual

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USB3382-AIC RDK
© PLX Technology, www.plxtech.com Page 4 of 34 06Aug12, version 1.3
2.19 Power Circuitry .................................................................................................................................................. 23
2.20 PCIe Protocol Debug ......................................................................................................................................... 24
2.21 WAKE# and Vaux Support .............................................................................................................................. 24
3 RDK CONFIGURATIONS .......................................................................................................... 25
3.1
x1x1 Add-In Card Strap Pin Setting .................................................................................................................... 25
3.2 x2 Add-In Card Strap Pin Setting ........................................................................................................................ 26
3.3 x1x1 Root Complex Mode Strap Pin Setting ....................................................................................................... 27
3.4 x2 Root Complex Mode Dipswitch Setting .......................................................................................................... 28
3.5 Configuration Modules ......................................................................................................................................... 29
3.6 Jumper Configurations ......................................................................................................................................... 29
4 APPENDIX ................................................................................................................................. 33
4.1 Board Revision Notes ............................................................................................................................................ 33
Figures
Figure 1. USB3382 RDK Front View _________________________________________________________________________ 7
Figure 2. Getting Started ‐ Addin Card Mode _____________________________________________________________________ 10
Figure 3. Getting Started –Root Complex Mode, Self Powered ______________________________________________________ 11
Figure 4. Getting Started ‐ Root Complex Mode, Bus Powered _______________________________________________________ 12
Figure 5. RDK Architecture __________________________________________________________________________________ 13
Figure 6. RDK Component Locations ___________________________________________________________________________ 15
Figure 7: USB 3.0 Standard B Port Cable and Receptacle __________________________________________________________ 16
Figure 8. Configuration Dipswitches ___________________________________________________________________________ 17
Figure 9. EEPROM in Socket _________________________________________________________________________________ 19
Figure 10. Pin Assignment of JTAG Port Header, JP1 _____________________________________________________________ 20
Figure 11. I2C Plug Orientation _______________________________________________________________________________ 20
Figure 12. Pin Assignment of I2C Connector JP2 _________________________________________________________________ 21
Figure 13: DB9 Male Connector ______________________________________________________________________________ 21
Figure 14. Fatal Error, INTA# and GPIO LEDs ____________________________________________________________________ 21
Figure 15. Manual PERST# button ____________________________________________________________________________ 22
Figure 16: 24 ‐ Pin ATX Power Connector ________________________________________________________________________ 23
Figure 17: Midbus 2.0 Probe Footprint _________________________________________________________________________ 24
Figure 18. x1x1 Add ‐ In Card Dipswitch Setting __________________________________________________________________ 25
Figure 19. x2 Add ‐ In Card Dipswitch Setting ____________________________________________________________________ 26
Figure 20. x1x1 Root Complex Mode Dipswitch Setting ___________________________________________________________ 27