PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
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3.7
ATX HD Power Connector (J1)
(See Section
2.8
for details)
Table 3-11. Pin assignment of J1
Pin Number
Signal Name
1 +12VDC
2 COM
(GND)
3 COM
(GND)
4 +5VCC
3.8
Reference Clock Header (J2)
(See Section
2.3
for details)
Table 3-12. Pin assignment of J2
Pin Number
Signal Name
1 RefClkp
(+)
2 GND
3 RefClkn
(-)
3.9
Probe Mode Input Header (J3)
This is for PLX use only.
Table 3-13. Pin assignment of J3
Pin Number
Signal Name In Schematics
1 GND
2 DB_SEL0_I
3 PWRFLT_B#_I
4 DB_SEL1_I
5 MRL_B#_I
6 PRSNT_B#_I
7 BUTTON_B#_I
8 GND
9 MRL_C#_I
10 BUTTON_C#_I
11 PWRFLT_C#_I
12 PRSNT_C#_I
13 GND
14 PWRGD_A_I
15 PWRGD_B_I
16 MRL_A#_I
17 BUTTON_A#_I
18 PWRFLT_A#_I
19 PRSMT_A#_I
20 GND
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