PLX Technology PEX 8624-AA RDK, Hardware Reference Manual

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PEX 8624-AA RDK Hardware Reference Manual – Version 1.1
Copyright © 2010 by PLX Technology, Inc. All rights reserved
9
PCI
Express
SLOT 1
VCC
System
power
supply
12V, 3.3V
VCC
VCC
Hot plug
controller
FETs
Hp_clken_b#
Hp_atnled_b#
Hp_pwrled_b#
Hp_pwren_b
Hp_perst_b#
Hp_button_b#
Hp_pwrflt_b#
Hp_mrl_b#
Hp_prsnt_b#
Hp_pwr_good_b
S2
D6
D7
TPS2311
(U6)
Pos1/SW3
Quad
2-to-1
Mux
(U7)
SN74LVC157
x8
Pwren
Perst#
Refclk
From refclk
buffer (U2)
Refclk
VCC
Pos2/SW3
HP_SL1_CTL
PEX 8624
(U1)
3.3V_SL1
D8
12V_SL1
D9 VCC VCC
VCC VCC
Refclk
Buffer
Clken#
Figure 2-6. PEX 8624-AA RDK PHP Circuits
Figure 2-6
shows the parallel hot-plug circuit. It includes a low cost TI dual hot–swap power controller TPS2311
(U6), a quad 2-to-1 multiplexer SN74LVC157 (U7), two International Rectifier power MOSFET IRF7470 (Q3 and
Q4), LEDs, manual switch, dipswitch and resistors. The manual switch (S1) connects to the HP_BUTTON_B#
input of the PEX 8624. It is used to generate the active low Hot-Plug attention button signal to the parallel hot-plug
controller. LEDs D6 and D7 represent the HP_ATNLED_B# (the attention LED) and HP_PWRLED_B# (power
LED) respectively on the parallel hot-plug controller. The PRSNT2# signal from SLOT 1 connects to the
HP_PRSNT_B# signal on the parallel hot-plug controller. This signal is used to detect when a PCI Express
adapter card is plugged into the connector SLOT 1. SW3 (position 1) is used to emulate the manually operated
retention latch sensor input HP_MRL_B# to the parallel hot-plug controller. When set to “ON” position, the internal
state machine of the parallel hot-plug controller is enabled. SW3 (position 2) is used to enable the power and
clock to SLOT 1. When set to the “ON” position, the active low signal HP_SL1_CTL on the multiplexer (U7) will
select HP_PWREN_B# to enable the hot-swap power controller (U6), HP_CLKEN_B# to enable the RefClk output
to connector SLOT 1, and the reset signal HP_PERST_B# to connector SLOT 1. Inversely when set to the “OFF”
position (SW3 position 2), the active high signal HP_SL1_CTL will bypass the Hot-Plug control outputs from the
parallel hot-plug controller and select another set of outputs to enable the hot-swap power controller (U6), and
enable the RefClk output and PERST# to connector SLOT 1.
When enabled, the hot-swap power controller (U6) monitors the 12V and 3.3V voltage supplies to SLOT 1. When
current levels exceed 5A, HP_PWRFLT# becomes active. Similarly, HP_PWR_GOOD_B becomes active when
lower than normal current levels are detected. PWRGD1 and PWRGD2 implement pull-up with external resistor.
Two additional LEDs, D8 and D9, are used to indicate 3.3V and 12V power at the connector SLOT 1.
2.5.2 Serial Hot-Plug Controller Circuits
PEX 8624-AA RDK also implements the serial hot-plug controller circuitry to PCI Express SLOT 2. By default, the
RDK is configured to bypass the serial hot-plug controller. In order to configure port 1 at PCI Express SLOT 2 as
a Serial Hot-Plug port with the port 0 is still a x4 upstream port, use the EEPROM to write 2’b00 to the bit [14:13]
of station 0’s Parallel Hop-Plug capable configuration register at offset 1E0h.