PCI 9656RDK- LITE Hardware Reference Manual v1.4
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© 2006 PLX Technology, Inc. All rights reserved.
2.1 System
Architecture
As shown in Figure 2-1, the RDK hardware
contains:
•
The PCI 9656 64-bit, 66 MHz PCI I/O
Accelerator
•
Four PCI 9656 Processor/Local Bus
components (CPLD, SRAM, Test
Headers, and POM connector)
•
Four hardware development modules
(LEDs, Flash ROM Socket, Reset
Circuitry, and RS232 Interface)
•
Large prototyping area
The RDK’s Processor/Local Bus is pre-
configured for non-multiplexed address and data
bus operation (C mode), but it is user
configurable for multiplexed address and data
operation (J Mode). (See Section 2.12 for details
on re-configuring the RDK hardware for J Mode
operation.) Once the board is correctly installed
into a PC computer system, a PCI master, such
as the motherboard’s processor, can perform
single memory read/write cycles, multiple
memory read/write cycles, and burst memory
read/write cycles from/to the on-board
synchronous SRAM in Direct Slave mode. The
microprocessor can also program the PCI 9656
I/O Accelerator to perform DMA data transfers
between the PCI bus and the SRAM.
Four hardware development modules in the
RDK provide the basic hardware building blocks
for PCI 9656-based generic bus designs.
Thirty (30) surface-mount footprints, two (2)
BGA footprints, and a 25x30, 0.1” through-hole
grid allow fast prototyping of processors, DSPs,
memory, I/O devices, etc.
2.2 PCI
9656
The PLX PCI 9656 is a 64-bit, 66 MHz PCI Bus
Master I/O Accelerator for PowerQUICC and
Generic 32-bit, 66 MHz Processor/Local Bus
designs. It is a PCI r2.2 and PICMG 2.1 r2.0
CompactPCI Hot Swap compliant device. It
features PLX’s Data Pipe Architecture
®
,
which
includes two DMA channels, Direct Slave and
Direct Master data transfer, EOT and Demand
Mode, and an Intelligent Messaging Unit. For
more detailed information about the PCI 9656,
please refer to the PCI 9656 Data Book.
2.3 Hardware
Memory
Map
The PCI 9656RDK-LITE board Processor/Local
Bus memory map is shown in Table 2-1.
Table 2-1. PCI 9656RDK-LITE Processor/Local Bus Memory Map
Hex Address
Range
Device
Chip Select
Comments
FFFF FFFF
5000 0000
Unused _ Available
4FFF FFFF
4000 0000
Unused CS3#
Available &
Re-programmable
3FFF FFFF
3000 0000
Unused CS2#
Available &
Re-programmable
2FFF FFFF
2000 0000
Unused CS1#
Available &
Re-programmable
1FFF FFFF
1000 0000
J mode POM connector
CS0#
32-bit, multiplexed
address/data bus
0FFF FFFF
0002 0000
Unused _ Available
0001 FFFF
0000 0000
Synchronous SRAM
32Kx32
SRAMCS#
8-, 16-, or 32-bit access
