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PCI 9656RDK- LITE Hardware Reference Manual v1.4 
© 2006 PLX Technology, Inc. All rights reserved.

 

 

11 

2.11 Power Supply 

The electronic devices on the RDK require 2.5V, 
3.3V, and/or 5V DC power. A 3A LDO regulator 
(U1) is used to convert the 5 V

DC

 to 3.3 V

DC

and a 2A LDO regulator (U2) is used to convert 
the 5 V

DC

 to 2.5 V

DC 

power for the on board 

devices. As long as the output current from the 
voltage converter remains less than the 
maximum current outputs from both LDOs, the 
RDK board will function correctly. 

2.12  RDK Mode Configuration 

The RDK hardware’s Processor/Local Bus is 
pre-configured for non-multiplexed data and 
address (C mode) Processor/Local Bus 
operation. It can be reconfigured for multiplexed 
data and address Processor/Local Bus 
operation (J mode). Several resistors configure 
the RDK hardware’s Processor/Local Bus for C 
or J Mode. The specific resistors to install and 
remove for each mode are detailed in Table 2-8. 
(‘X’ means installed; no ‘X’ means removed.)

 

Table 2-8. RDK Board Mode Configuration 

Resistors 

Value 

C Mode 

(Default) 

J Mode 

Mode Pins Configuration 

 

 

 

R4 

1/10w, 10K ohm, 5% 

 

R5 

1/10w, 10K ohm, 5% 

 

 

R6 

1/10w, 0 ohm, 5% 

 

R7 

1/10w, 0 ohm, 5% 

Data/Address Pins Configuration 

 

 

 

R46 

1/10w, 10K ohm, 5% 

 

R47 

1/10w, 10K ohm, 5% 

 

R48 

1/10w, 10K ohm, 5% 

 

R49 

1/10w, 10K ohm, 5% 

 

R50 

1/10w, 10K ohm, 5% 

 

R51 

1/10w, 10K ohm, 5% 

 

R71 

1/10w, 10K ohm, 5% 

 

R79 

1/10w, 10K ohm, 5% 

 

R93 

1/10w, 10K ohm, 5% 

 

R94 

1/10w, 10K ohm, 5% 

 

R95 

1/10w, 10K ohm, 5% 

 

R96 

1/10w, 10K ohm, 5% 

 

R97 

1/10w, 10K ohm, 5% 

 

R98 

1/10w, 10K ohm, 5% 

 

R99 

1/10w, 10K ohm, 5% 

 

R100 

1/10w, 10K ohm, 5% 

 

R101 

1/10w, 10K ohm, 5% 

 

R102 

1/10w, 10K ohm, 5% 

 

R103 

1/10w, 10K ohm, 5% 

 

R104 

1/10w, 10K ohm, 5% 

 

R105 

1/10w, 10K ohm, 5% 

 

R106 

1/10w, 10K ohm, 5% 

 

R107 

1/10w, 10K ohm, 5% 

 

R108 

1/10w, 10K ohm, 5% 

 

Summary of Contents for PCI 9656RDK-LITE

Page 1: ...PCI 9656RDK LITE Hardware Reference Manual...

Page 2: ......

Page 3: ...PCI 9656RDK LITE Hardware Reference Manual Version 1 4 January 2006 Website http www plxtech com Technical Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Page 4: ...to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registere...

Page 5: ...sibility for damage or loss resulting from the use of this manual for loss or claims by third parties which may arise through the use of the Rapid Development Kit RDK or for any damage or loss caused...

Page 6: ......

Page 7: ...1 Serial EEPROM Contents 5 2 5 Synchronous Burst SRAM 7 2 6 Xilinx CPLD 7 2 7 Test Headers 7 2 8 PLX Option Module Connector 7 2 9 Hardware Modules 7 2 9 1 RS 232 Interface 7 2 9 2 Debug and Status LE...

Page 8: ...rototyping Diagram 9 LIST OF TABLES Table 2 1 PCI 9656RDK LITE Processor Local Bus Memory Map 4 Table 2 2 Long Serial EEPROM Load Registers 5 Table 2 3 Extra Long Serial EEPROM Load Registers 6 Table...

Page 9: ...ith the PCI 9054RDK LITE simplifying the migration of existing 32 bit 33 MHz PCI designs into 64 bit 66 MHz PCI products PLL U1 LDO U2 LDO 16 pin SOIC 16 pin SOIC U10 LAH5 LAH6 osc DB9 LAH4 LAH3 s1 BG...

Page 10: ...demonstrates the PCI 9656 continuous burst feature One 1 power on LED and four 4 user defined status debug LEDs Built in DB9 connector and programmable DTE DCE RS 232 transceiver for adding a serial...

Page 11: ...Address Bus Data bus Control Bus POM Connector Test Headers Prototyping Area Footprints Hardware Modules RS232 Transceiver Reset Circuit User Defined LEDs Flash ROM Socket Synchronous SRAM 32Kx32 SRAM...

Page 12: ...e RDK provide the basic hardware building blocks for PCI 9656 based generic bus designs Thirty 30 surface mount footprints two 2 BGA footprints and a 25x30 0 1 through hole grid allow fast prototyping...

Page 13: ...f Mailbox 1 User Defined MBOX1 15 0 14h FFFE MSW of Range for PCI to Local Address Space 0 LAS0RR 31 16 16h 0000 LSW of Range for PCI to Local Address Space 0 LAS0RR 15 0 18h 0000 MSW of Local Base Ad...

Page 14: ...Hex Value Description Register Bits Affected 44h 9656 Subsystem ID PCISID 15 0 46h 10B5 Subsystem Vendor ID PCISVID 15 0 48h FFFE MSW of Range for PCI to Local Address Space 1 LAS1RR 31 16 4Ah 0000 LS...

Page 15: ...rs and LHOLDA to the PCI 9656 The chip select generator in the CPLD generates the SRAM chip select SRAMCS and four additional active low chip selects for the Processor Local Bus devices The chip selec...

Page 16: ...ure the RDK reset circuitry for user defined reset and Power Management Event request generation Table 2 5 Reset Circuit Configuration R41 installed User defined reset circuit default R40 R43 not inst...

Page 17: ...Land Socket and plug the Land Socket to the Minigrid Socket Note The size of each hole on BGA1 is 0 0165 in diameter The holes are large enough to accept the 0 014 diameter Land Socket pins They are t...

Page 18: ...ADS 2104L 80 pin PQFP 2 0 5mm PPC401GF 84 pin PLCC 1 0 05 CPLDs MIPS CPUs PPC401GF 100 pin PQFP 2 0 5mm CPLDs TI 320 C541 LC541 LC543 LC546 ADSP 2186L 112 pin PQFP 1 0 65mm SH7032 7034 7040 128 pin P...

Page 19: ...veral resistors configure the RDK hardware s Processor Local Bus for C or J Mode The specific resistors to install and remove for each mode are detailed in Table 2 8 X means installed no X means remov...

Page 20: ...he SRAM For example el s0 11111111 el s0 4 22222222 el s0 8 33333333 el s0 c 44444444 el s0 10 55555555 el s0 14 66666666 el s0 18 77777777 el s0 1c 88888888 c Click the DMA button on PLXMon to open t...

Page 21: ...RAM cycle 10 22 2004 Changed two bufifo statements after defining the internal variables to call the Xilinx s BUFE macro timescale 1ns 100ps module sramctr9x56 clk adsn blastn lwdrdn lhold lbr lben ad...

Page 22: ...b0010 4 b1101 adds_4msb 4 b0011 4 b1011 adds_4msb 4 b0100 4 b0111 4 b1111 byte enable encode for SRAM write cycles wire 3 0 sram_bwn lwdrdn a31_28 b1_0000 lben 3 0 4 b1111 store the upper address LA31...

Page 23: ...dds 9 2 1 sramoen 1 sramcsn 1 oer b1 oeb b1 state s0 end else if lwdrdn blastn begin if sram_adds 9 2 hfe begin oeb b0 sram_adds 9 2 sram_adds 9 2 1 state s3 end else begin sram_adds 9 2 sram_adds 9 2...

Page 24: ...s 9 2 hff begin oeb b0 sram_adds 9 2 sram_adds 9 2 1 state s3 end else begin sram_adds 9 2 sram_adds 9 2 1 sramoen 0 sramcsn 0 oer b0 oeb b1 state s2 end end s3 begin sramcsn 1 oer b1 oeb b1 state s0...

Page 25: ...ectec Sales 408 764 0600 All America 1800 573 2727 U4 5 1 Fairchild Semi FDN335N IC N channel 2 5V MOSFET SSOT 3 SMT Arrow Electronics U5 6 1 PLX PCI 9656 BA66BI or PCI 9656 BA66BES IC PCI I O acceler...

Page 26: ...Panasonic ERJ 6GEYJ151V Res 1 10W 150 ohm 5 SMT 0805 Digi Key R32 R36 29 11 Panasonic ERJ 6GEYJ102V Res 1 10W 1K 5 SMT 0805 Digi Key R58 R66 R116 R117 30 1 Panasonic ERJ 6GEYJ392V Res 1 10W 3 9K 5 SMT...

Page 27: ...SC70 EIAJ SC88 1 25mm wide Arrow Electronics U15 24 0 CTS 742 08 3 103 J BK Res Network 10K 5 4R isolated SMT Ccase Digi Key RN22 RN24 25 0 Panasonic ERJ 6GEYJ0R0V Res 1 10W zero ohm 5 SMT 0805 Digi...

Page 28: ...PCI 9656RDK LITE Hardware Reference Manual v1 4 20 2006 PLX Technology Inc All rights reserved...

Page 29: ...Connector PG 5 000 Reset Circuit PG5 Up to 32 bit 66MHz 64 bit 66MHz 10 5 2001 Released to production 100 5 6 2002 Modified IDDQEN circuit changed R92 to 10K pull up to 2 5V removed LA28 pull down R91...

Page 30: ...3 3 VIN 3 GND 1 VOUT 2 J1 PCICONUNV_64bit TRST A1 12V B1 12V A2 TCK B2 TMS A3 GND B3 TDI A4 TDO B4 5V A5 5V B5 INTA A6 5V B6 INTC A7 INTB B7 5V A8 INTD B8 RESERVED A9 PRSNT1 B9 VIO A10 RESERVED B10 RE...

Page 31: ...R90 10K R71 10K R11 10K R17 10K C33 0 1uF RN4 742 08 3 103 J XX 1 2 3 4 5 6 7 8 R18 10K R15 22 RN12 742 08 3 103 J XX 1 2 3 4 5 6 7 8 R8 10K U10 93CS56L or 66L 8DIP Socket CS 1 SK 2 DI 3 DO 4 VCC 8 P...

Page 32: ...R70 10K R109 0 U13 XC9572XL 5TQ100C IOA1 16 IOA2 13 IOA3 18 IOA4 20 IOA5 14 IOA6 15 IOA7 25 IOA8 17 IOA9 28 IOA11 33 IOA12 36 IOA13 29 IOA14 39 IOA15 30 IOA16 40 IOB1 87 IOB2 94 IOB3 91 IOB4 93 IOB5 9...

Page 33: ...PB2 R30 0 PB22 PB3 R31 0 PB23 PB5 PB4 PB41 FP31 32 pin PLCC CE 22 OE 24 WE 31 I O0 13 I O1 14 I O2 15 I O3 17 I O4 18 I O5 19 I O6 20 I O7 21 VCC 32 GND 16 A17 30 A16 2 A15 3 A14 29 A13 28 A12 4 A11...

Page 34: ...2 LA22 LA23 LA31 LA20 LA26 LA16 LA2 LA8 LA10 LA17 LA11 LA5 LA25 LA4 LA24 LA20 LA27 LA15 LA19 LA13 LA10 LA29 LA21 LA21 LA19 LA26 LA16 LA4 LA11 LA31 LA29 LA7 LA14 LA22 LA28 LA18 LA23 LA17 LA12 LA12 LA13...

Page 35: ...PF94 PC11 PE25 PF30 PF63 PC60 PF169 PF98 PC10 PE24 PF26 TB5 HEADER 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PF69 PC61 PF162 PF93 PC17 PE33 PF25 TB1 HEADER 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18...

Page 36: ...4 PG203 PG202 PG201 PG200 PG199 PG223 PG222 PG 1 240 9 PG32 PG141 PG93 PG193 PG20 PG142 PG78 PG194 PG43 PG143 PG69 PG195 PG28 PG144 PG89 PG196 100 Pin TQFP FP17 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 10...

Page 37: ...PG201 PG202 PG203 PG204 PG205 PG206 PG207 PG208 PG209 PG210 PG211 PG212 PG213 PG214 PG215 PG216 PG217 PG218 PG219 PG220 PG 1 240 PG 1 240 8 FP20 144 Pin TQFP Footprint 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8...

Page 38: ...PH186 PH150 PH138 PH138 PH84 PH179 PH143 PH20 PH2 PH37 PH38 PH53 PH122 PH123 PH154 PH171 PH172 PH202 PH203 PH 1 208 11 PH21 PH132 PH71 PH182 PH1 PH133 PH51 PH183 PH47 PH134 PH97 PH184 PH32 PH135 PH82...

Page 39: ...72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 80 80 81 81 82 82 83 83 84 84 85 85 86 86 87 87 88 88 89 89 90 90 91 91 92 92 93 93 94 94 95 95 96 96 97 97 98 98 99 99 100 100 101 101 102 102 103 103...

Page 40: ...PI125 PI126 PI127 PI128 PI129 PI130 PI131 PI132 PI133 PI134 PI135 PI136 PI137 PI138 PI139 PI140 PI141 PI142 PI143 PI144 PI145 PI146 PI147 PI148 PI149 PI150 PI151 PI152 PI153 PI154 PI155 PI156 PI 1 160...

Page 41: ...ole Prototype Area FP29 FP30 54 pin TSOP 54 pin TSOP JP1 208 144 80 pin QFP FP18 FP20 0 5mm pitch on the back 176 100 pin QFP FP24 FP25 0 5mm pitch on the back 128 pin 0 4mm pitch TQFP on the back RJ4...

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