2. HARDWARE ARCHITECTURE
This section provides a detailed description of the hardware included in the PCI 9656RDK-LITE.
Figure 2-1 shows the RDK hardware block diagram.
PCI 9656
Address/Data
Bus
Control Bus
Serial
EEPROM
Local Bus
Clock Circuit
66MHz
LOCAL BUS
32-bit, up to 66MHz
PCI BUS
64-bit, 66MHz
Address Bus
Data bus
Control Bus
POM
Connector
Test
Headers
Prototyping
Area &
Footprints
Hardware Modules
RS232 Transceiver
Reset Circuit
User Defined LEDs
Flash ROM Socket
Synchronous
SRAM
32Kx32
SRAM
Controller
Data Bus
Ready#
Memory
Address
Bus
Control
7
32
8
SRAM Controller
Local Bus
Arbiter
Chip Select
Generator
Control
8
Address
Xilinx CPLD
Bterm#
Figure 2-1. PCI 9656RDK-LITE Hardware Block Diagram
PCI 9656RDK- LITE Hardware Reference Manual v1.4
© 2006 PLX Technology, Inc. All rights reserved.
3
