Pixelink PL-A630, System Manual

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P
AGE
12
A
PPENDIX
A. G
LOSSARY
Enhanced
Control Header
Pin 16
Pin 1
Pin 2
External Power
Header
Fi s shown)
PL-A653/PL-A654 Pinout of the Enhanced C
gure 2.9 Enhanced Control/External Power Headers (may not be exactly a
Table 2.2 ontrol Header
Pin Pin Name Function
1 TRIGGER Trigger—3.3 V or 5 V TTL or high-to-low transition triggers image capture.
Refer to PixeLINK API function PimMegaReturnFrameAfterTrigger .
CMOS input;
2 GND Ground
3 HC a bo eset the imaging /RESET Reset—5 V
module. MOS sign l output low for a ut 200 milliseconds at power-up to r
4 GND Ground
5 urpose 5 output.
Refer to PixeLINK API functions PimMegaGetGpo and PimMegaSetGpo.
GP1 General p output— V HCMOS
6 GND Ground
7 FLASH External flash—5 VHCMOS
Refer to PixeLINK API funct output; active high pulse.
ions PimMegaCaptureFrameToBitmap and PimMegaReturnStillFrame .
8 GND Ground
9 SH control device—5 V HCMOS outp UTTER Shutter ut; active high pulse.
Refer to the PixeLINK API functions PimMegaCaptureFrameToBitmap and
PimMegaReturnStillFrame .
10 GND Ground
11 GP2 General purpose output—5 V HCMOS output.
Refer to the PixeLINK API functions
PimMegaGetGpo and PimMegaSetGpo .
12
GND Ground
13 VSYNC Vertical synchronization—5 V HCMOS output; active high.
14 GND Ground
15 SCL I²C interface clock —5 V HCMOS buffered output.
16 SDA I²C interface data—3.3 V HCMOS level unbuffered bi-directional signal.
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