PDP-434CMX
144
1
2
3
4
1
2
3
4
C
D
F
A
B
E
HS_DJTR
1
PD#
2
SDA (ST)
3
PIXS
4
GND
5
VCC
6
I2C_MODE#
(STAG_OUT#)
7
SCDT
8
PDO#
9
QE0
10
QE1
11
QE2
12
QE3
13
QE4
14
QE5
15
QE6
16
QE7
17
OVCC
18
OGND
19
QE8
20
QE9
21
QE10
22
QE11
23
QE12
24
QE13
25
QE
14
26
QE
15
27
OG
N
D
28
OV
C
C
29
QE
16
30
QE
17
31
QE
18
32
QE
19
33
QE
20
34
QE
21
35
QE
22
36
QE
23
37
VCC
38
GND
39
CT
L
1
40
CT
L
2
41
CT
L
3
42
OV
C
C
43
ODCK
44
OG
N
D
45
DE
46
VS
YN
C
47
HS
YNC
48
QO0
49
QO1
50
75
QO21
74
QO20
73
QO19
72
QO18
71
QO17
70
QO16
69
GND
68
VCC
67
QO15
66
QO14
65
QO13
64
QO12
63
QO11
62
QO10
61
QO9
60
QO8
59
OGND
58
OVCC
57
QO7
56
QO6
55
QO5
54
QO4
53
QO3
52
QO2
51
QO22
SC
L
(O
CK
_INV
)
10
0
MO
D
E
99
PGND
98
PVC
C
97
EX
T
_
RE
S
96
AV
C
C
95
RX
C-
94
RXC+
93
AG
ND
92
RX
0
-
91
RX
0+
90
AG
ND
89
AV
C
C
88
AG
ND
87
RX
1
-
86
RX
1+
85
AV
C
C
84
AG
ND
83
AV
C
C
82
RX
2
-
81
RX
2+
80
AG
ND
79
OVC
C
78
QO
2
3
77
OGND
76
DIFFERENTIAL
SIGNAL
ODD 8-
b
it
s
RED
EVEN 8-bits RED
ODD 8
-b
it
s
GREE
N
EV
EN
8
-bi
ts
G
R
EEN
O
DD 8
-bi
ts BL
UE
EV
EN
8
-bi
ts
B
L
U
E
CO
N
F
IG
. PI
NS
PLL
PW
R
MGM
T
GPO
OUTP
UT
CL
O
C
K
CONTROLS
Pin Arrangement (Top View)
SII116BCTG100 (AV I/O ASSY : IC7503)
• Panel Link Receiver IC