Pioneer CDJ 1000MK3 - Professional CD/MP3 Turntable, Service Manual

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CDJ-1000MK3
101
5 6 7 8
5 6
7
8
C
D
F
A
B
E
No. Pin Name Signal Name I/O Pin Function
96 CS0 XCS0 O Area 0 chip select
97 VccQ V+3R3
−
Power supply for I/O (3.3V)
98 CS2 XCS2 O
Area 2 chip select
99 CS3 XCS3 O
Area 3 chip select
100 CS4 XCS4 O Area 4 chip select
101 CS5 XCS5 O
Area 5 chip select
102 CS6 XCS6 O
Area 6 chip select
103 CE2A N.C.
−
Not used
104 CE2B N.C.
−
Not used
105 CKE CKE O CK enable (SDRAM)
106 RAS3L XRAS3L O
RAS3L (SDRAM)
107 RAS2L N.C.
−
Not used
108 CASLL XCASLL O CASL (SDRAM)
109 VssQ GND
−
GND
110 CASLH MOT_RST O Reset output of Motorola DSP (reset with H)
111 VccQ V+3R3
−
Power supply for I/O (3.3V)
112 CASHL TI_RST O
Reset output for TI DSP (reset with H)
113 CASHH N.C.
−
Not used
114 DACK0 XDACK0
−
Not used (connect to FPGA)
115 DACK1 XDACK1
−
Not used (connect to FPGA)
116 CAS2L N.C.
−
Not used
117 CAS2H N.C.
−
Not used
118 RAS3U DAXLAT O DAC latch signal
119 RAS2U MUTE O Audio output stage mute (H: Mute on)
120 TDO TDO
−
For development
121 BACK N.C.
−
Not used
122 BREQ
−
I
Bus request (Not used, pullup with 3.3V)
123 WAIT XWAIT I
Hardware wait request (FPGA)
124 RESETM
−
I
Manual reset (Not used, pullup with 3.3V)
125 PTH FPGA_DONE I DONE signal for FPGA configuration
126 IOIS RY/XBY I Connect to flash ROM
127 ASEMD0 ASEMD0
−
For development
128 ASEBRKAK XASKAK
−
For development
129 PTG FPGA_XINIT I
INIT signal for FPGA configuration
130 AUDATA3 AUDATA3
−
For development
131 AUDATA2 AUDATA2
−
For development
132 Vss GND
−
GND
133 AUDATA1 AUDATA1
−
For development
134 Vcc V+1R8
−
Power supply for core (1.8V)
135 AUDATA0 AUDATA0
−
For development
136 TRST XTRST
−
For development
137 TMS TMS
−
For development
138 TDI TDI
−
For development
139 TCK TCK
−
For development
140 PINT11
− −
Not used
141 PINT10
− −
Not used
142 PINT9 UPDATE
−
For development
143 PINT8 MOT EMPTY I Motorola FIFO empty signal input (High with EMPTY)
144 MDO SHMD0 I Clock mode setting (pull up with 3.3V)
145 Vcc-PLL1 V+1R8
−
Power supply for PLL1