31
Description of the ERROR Register
Description of the ERROR Register
Description of the ERROR Register
Description of the ERROR Register
The following list contains a description of the individual bits of the ERROR register. A “1” as a bit
leads to a deactivation of the drivers output.
The Bits 0 and 1 are cleared every time the ENABLE pin is set low or when the CLEAERROR command
is used.
The Bits 6 and 7 are set during the power on self test. They can not be cleared by the ENABLE pin or
the CLEARERROR command. If one of these bits is set, the supply voltage should be switch off and on
again. If the error persists, the LDP-CW needs to be repaired.
Bit
Bit
Bit
Bit Name
Name
Name
Name
R / W
R / W
R / W
R / W
Meaning
Meaning
Meaning
Meaning
0
DRV_OVERTEMP
Read
Indicates an over temperature shutdown of the output
stage.
1
DRV_FAIL
Read
Indicates a shutdown of the LDP-CW due to a load failure
or an over current
2
reserved
Read
Reserved
3
TEC_SWITCH_FAIL
Read
This bit indicates that the mode switch was switched while
the power was turned on.
4
CFG_CHKSUM_FAIL
Read
Indicates that the internal configuration register is corrupt.
If this error persists, the TEC needs to be repaired.
5
reserved
Read
Reserved
6
CAL_CHKSUM_FAIL
Read
Indicates that the internal calibration registers are corrupt.
If this error persists, TEC needs to be repaired.
7
DEF_CHKSUM_FAIL
Read
Indicates that the internal default registers are corrupt. The
default values should be re- saved.
8
TEC_ADC_FAIL
Read
This bit indicates a internal error. If this bit persists, TEC
needs to be repaired.
9-
31
Reserved
Read
Reserved
