phyCORE-P8xC51Mx2
26
PHYTEC MMesstechnikGmbH 2005 L-602e_3
RAM-SW:
Two SRAM devices of 128 kByte capacity each can
populate the phyCORE-P8xC51Mx2. Setting the
RAM-SW bit allows mapping of the second RAM’s
address space (/CSRAM2) into the range
02:0000h - 03:FFFFh. If the bit is erased then the
address range for the second RAM is
08:0000h - 09:FFFFh.
This procedure allows configuration of one continouos
address space for both SRAM devices.
VN-EN:
This bit enables selection of von Neumann memory
within the entire address space of the controller. RAM
is mapped to both CODE and DATA memory in this
memory model. The Flash memory is accessible in the
address range 20:0000h – 3F:FFFFh.
Following a hardware reset, the Harvard
default. The von Neumann memory is especially useful when
programming code is to be downloaded and subsequently run during
runtime, as is the case with a Monitor program.
1
:
Memory space in which no difference is made between CODE and XDATA access. This
means that both accesses use the same physical memory device, usually a RAM.
2
:
Memory space in which CODE and XDATA accesses use physical different memory devices.
CODE access typically uses a ROM or Flash device, whereas XDATA access uses a RAM.
