Phytec phyCORE-P8xC51Mx2 Hardware Manual Download

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phyCORE-P8xC51Mx2



PHYTEC MMesstechnikGmbH 2005 L-602e_3

3.13

J20 Remote Download Source

Space U10 on the module is intended for mounting the Remote
Supervisory Chip. This IC can initiate a boot sequence via various
serial interfaces (refer to section 10). Jumper J20 is reserved for
future use and remains open as default.

The following configurations are possible:

Download Source

J20

Not available

open

RxD0

1 + 2*

I²C – SDA

2 + 4

RS-232 / RS-485 – RxD1

2 + 3

*= Default setting

Table 15:

J20 Remote Download Source Configuration

___________________

The Remote Supervisor IC is under development. Hence Jumper J20 has no function at

this time

Summary of Contents for phyCORE-P8xC51Mx2

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE P8xC51Mx2 Hardware Manual Edition April 2005...

Page 2: ...TEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further rese...

Page 3: ...erface 19 3 8 J12 J13 Pins X1F13 X1E14 Configuration 19 3 9 J14 RS 485 Interface Control 20 3 10 J15 J18 EEPROM Configuration 20 3 11 J16 J17 Configuration of P1 6 and P1 7 for I2C Bus 21 3 12 J19 RTC...

Page 4: ...Settings 48 14 3 Functional Components on the phyCORE Development Board LD 5V 49 14 3 1 Power Supply at X1 49 14 3 2 Starting FlashTools 51 14 3 3 First Serial Interface at Socket P1A 53 14 3 4 Power...

Page 5: ...n of the I O Area 29 Figure 11 Physical Dimensions not Shown at Scale 39 Figure 12 Modular Development and Expansion Board Concept with the phyCORE P8xC51Mx2 44 Figure 13 Location of Connectors on the...

Page 6: ...1 Pins 1 and 23 Connections 16 Table 5 J4 PLD Control 17 Table 6 J5 J6 RAM Selection and Mode 17 Table 7 J7 SRAM Supply Voltage 18 Table 8 J8 J9 Port P3 0 and P3 1 1st Serial Interface Configuration 1...

Page 7: ...of the DB 9 Socket P1B 56 Table 29 Improper Jumper Settings for Configuration of P1B 57 Table 30 Jumper Configuration for Plug P2A 58 Table 31 Improper Jumper Settings for Plug P2A 59 Table 32 Jumper...

Page 8: ...ORE P8xC51Mx2 PHYTEC Messtechnik GmbH 2005 L 602e_3 Table 39 Unused Pins on the phyCORE P8xC51Mx2 Development Board Expansion Board 68 Table 40 JP19 Jumper Configuration for Silicon Serial Number Chip...

Page 9: ...r the PHYTEC phyCORE P8xC51Mx2 PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e for use as a test and prot...

Page 10: ...of a series of PHYTEC Single Board Computers SBCs that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports all common 8 and 16 bit contro...

Page 11: ...lems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package The increased pin package allows...

Page 12: ...orts extend from the controller to standard width 2 54 mm 0 1 in pin header rows aligning two sides of the board allowing it to be plugged like a big chip into a target application Precise specificati...

Page 13: ...pins aligning two sides of the board enabling it to be plugged like a big chip into target applications 256 kByte to 2 MB external Flash on board enabling In System Programming ISP with PHYTEC FlashTo...

Page 14: ...P S 8xC51Mx2 P2 Cntrl p h y C O R E C o n n e c t o r Transceiver R S 2 3 2 analog In ports C n t r l A d d r F L A S H 256KB 2MB R A M 128 KB 1MB S1 P0 D a t a Transceiver R S 4 8 5 Transceiver R S...

Page 15: ...on it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 3 indicates all cont...

Page 16: ...phyCORE connector header pins pointing down or with the socket of the phyCORE Development Board LD 5V target circuitry The upper left hand corner of the numbered matrix Pin 1A is thus covered with th...

Page 17: ...h when plugged onto the Development Board does not span the entire length of the receptacle socket The phyCORE Development Board LD 5V can house all phyCORE modules with standard width 2 54 mm 0 10 in...

Page 18: ...oded Chip Select signal 2 5A RD O RD signal 6A 7A 8A 9A A0 A3 A5 A7 O Address bus from address latch A0 A3 A5 A7 10A 11A 12A A10A18 A12A20 A15 O Address bus upper address lines from C 13A 14A 15A AD1...

Page 19: ...s lines from C 12C 13C 4C 15C AD0 AD2 AD5 AD7 I O Multiplexed address data bus C 16C 17C 18C A18 A20 A22 O Upper address lines from address latch 2 A18 A20 A22 Pin Row X1D 1D VCC Voltage input 5 VDC 2...

Page 20: ...e RS 485 transceiver or RxD1 input of the RS 232 transceiver 16E SDA I O I2 C data Pin Row X1F 1F 2F 3F GND Ground 0 V 4F PFI I Power Fail Input of Reset IC 5F PF0 O Power Fail Output of Reset IC 6F R...

Page 21: ...elivery Figure 5 illustrates the numbering of the jumper pads while Figure 6 and Figure 7 indicate the location of the jumpers on the board With the exception of Jumper J18 all solder jumpers Jxx are...

Page 22: ...phyCORE P8xC51Mx2 14 PHYTEC MMesstechnikGmbH 2005 L 602e_3 Figure 7 Location of the Jumpers Bottom View...

Page 23: ...nected to RS 232 transceiver 2 3 P4 0 and P4 1 connected to RS 485 transceiver J12 J13 1 2 second serial interface as RS 232 X1E14 X1F13 2 3 second serial interface as RS 485 X1E14 X1F13 J14 open RS 4...

Page 24: ...memory 1 2 from internal program memory 2 3 Default setting Table 3 J1 Access to External or Internal Program Memory 3 2 J2 J3 Pin 1 and Pin 23 on U1 On some controllers populating space U1 pins 1 an...

Page 25: ...PLD Mode J4 PLD enabled 1 2 PLD disabled 2 3 Default setting Table 5 J4 PLD Control 3 4 J5 J6 RAM Selection Both standard RAM types or high speed devices can populate the phyCORE P8xC51Mx2 at U5 and...

Page 26: ...sible SRAM Supply Voltage J7 VCCRAM connected to VCC 1 2 VCCRAM connected to VPD 2 3 Default setting Table 7 J7 SRAM Supply Voltage 3 6 J8 J9 P3 0 and P3 1 as RxD0 and TxD0 Signals Jumpers J8 and J9 c...

Page 27: ...nterface J10 J11 P4 0 and P4 1 as RS 232 1 2 1 2 P4 0 and P4 1 as RS 485 2 3 2 3 P4 0 and P4 1as port pins open open Default setting Table 9 J10 J11 Port P4 0 and P4 1 2nd Serial Interface Configurati...

Page 28: ...er inactive P1 5 as port pin open Default setting Table 11 J14 RS 485 Interface Control Configuration 3 10 J15 J18 EEPROM Configuration1 Jumper J18 determines the size of the EEPROM populating U12 The...

Page 29: ...as I O pin open Port P1 6 used as I C SCL closed Default setting Table 13 J16 and J17 I C Interface Configuration 3 12 J19 RTC Interrupt Jumper J19 determines if the interrupt output of the RTC U13 e...

Page 30: ...ous serial interfaces refer to section 10 Jumper J20 is reserved for future use and remains open as default The following configurations are possible Download Source J20 Not available open RxD0 1 2 I...

Page 31: ...ss decoder by means of two internal Control Registers Both registers are carried out as write only registers with access through the controller s XDATA memory space There are two distinct address area...

Page 32: ...0 0 0 H 1 2 8 k B S R A M 1 2 8 k B S R A M U 6 U 5 5 1 2 k B S R A M U 6 5 1 2 k B S R A M U 5 1 2 8 k B S R A M U 6 U 5 R A M S W 1 R A M S W 0 I O I O I O S W 0 C S 3 0 0 F F 0 0 h 0 0 F F F F h C...

Page 33: ...se of its special restrictions In this model write access to the Flash is possible within the address area 20 0000H 30 0000H Note This bit must only be set when the von Neumann memory model is enabled...

Page 34: ...ce of the controller RAM is mapped to both CODE and DATA memory in this memory model The Flash memory is accessible in the address range 20 0000h 3F FFFFh Following a hardware reset the Harvard2 archi...

Page 35: ...1 2 8 k B S R A M U 6 U 5 R A M S W 1 R A M S W 0 I O I O S W 0 C S 3 0 0 F F 0 0 h 0 0 F F F F h C S 2 0 0 F E 0 0 h 0 0 F E F F h C S 1 0 0 F D 0 0 h 0 0 F D F F h C S R E G 0 0 F C 0 0 h 0 0 F C F...

Page 36: ...ware reset the I O area is accessible in the range between FC00H FFFFH Setting bit IO SW 1 maps the I O area to 3F FC00H 3F FFFFH This I O area generally consists of 4 blocks of 256 bytes each In thre...

Page 37: ...In order to ensure proper functioning of FlashTools firmware enabling on board programming of the Flash memory it is essential that the CS REG signal be used as described herein These internal regist...

Page 38: ...hake signal communication However depending on user needs handshake communication can be replicated using port pins on the microcontroller Use of an RS 232 signal level in support of handshake communi...

Page 39: ...ell as subsequent erasure and reprogramming of user code into the Flash with the help of an intuitive PC side software The FlashTools firmware portion resides in the initial 32 kByte of Flash memory w...

Page 40: ...of the Flash device as during the Flash s internal programming process the reading of data from Flash is not possible For Flash programming program execution must be transferred out of Flash such as...

Page 41: ...that require frequent and fast storage of a large amount of data other memory devices can populate U12 Modern I C FRAMs with approximately 1010 write and erase cycles can be used for this purpose Thes...

Page 42: ...hyCORE P8xC51Mx2 is equipped with a battery the Real Time Clock runs independently of the module s power supply Programming of the Real Time Clock is done via the I2 C bus at address 1010001 0 0xA2 co...

Page 43: ...upted The basic characteristics of this controller are described in the appropriate Data Sheet which is available on the Spectrum CD All pins of the Reset controller are routed to the phyCORE connecto...

Page 44: ...initiate a boot sequence via a serial interface such as RS 232 or RS 485 The RSC can start PHYTEC FlashTools without requiring a manual reset of the phyCORE module via a Boot jumper or button This ena...

Page 45: ...battery must connect to GND on the phyCORE P8xC51Mx2 As of the printing of this manual a lithium battery is recommended as it offers relatively high capacity at low discharge In the event of a power...

Page 46: ...phyCORE P8xC51Mx2 38 PHYTEC MMesstechnikGmbH 2005 L 602e_3...

Page 47: ...xC51Mx2 are represented in Figure 11 The module s profile is approximately 11 mm thick with a maximum component height of 3 5 mm on the back side of the PCB and approximately 6 mm on the front side Th...

Page 48: ...t condensed Operating voltage 5 V 5 VBAT 3 V 20 Power consumption maximum 220 mA typically 170 mA at 12 MHz oscillator frequency and 1 MB SRAM at 20 C Power consumption with battery buffer maximum 100...

Page 49: ...oscillator is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged whil...

Page 50: ...phyCORE P8xC51Mx2 42 PHYTEC MMesstechnikGmbH 2005 L 602e_3...

Page 51: ...Computer module The Development Board design allows easy con nection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation Thi...

Page 52: ...board signals provided by the SBC module mounted on the Development Board are broken out 1 1 to the expansion board by means of its patch field 7 The required connections between SBC module Developmen...

Page 53: ...ty X2 mating receptacle for expansion board connectivity P1 dual DB 9 sockets for serial RS 232 interface connectivity P2 dual DB 9 connectors for CAN or RS 485 interface connectivity X4 voltage suppl...

Page 54: ...s on the phyCORE Development Board LD 5V Peripheral components of the phyCORE Development Board LD 5V can be connected to the signals of the phyCORE P8xC51Mx2 by setting the applicable jumpers The Dev...

Page 55: ...CORE Development Board LD 5V with the standard phyCORE P8xC51Mx2 standard P8xC51Mx2 controller use of the first and second RS 232 interface LED D3 the Boot button on the Development Board Jumper setti...

Page 56: ...using the phyCORE P8xC51Mx2 only one main supply voltage is required VCC1 with 5V The connector pins for a second supply voltage on the phyCORE P8xC51Mx2 are not defined Sockets G and H on the phyCORE...

Page 57: ...pply power to the Development Board Power spikes during power on could destroy the phyCORE module mounted on the Development Board Do not change modules or jumper settings while the Development Board...

Page 58: ...module is used JP9 open phyCORE P8xC51Mx2 not connected to main supply voltage Table 21 JP9 Improper Jumper Settings for the Main Supply Voltage Correct setting of Jumper JP9 depends on the available...

Page 59: ...to a high level signal at the time the Reset signal changes from its active to the inactive state The phyCORE Development Board LD 5V provides three different options to enable the Flash programming...

Page 60: ...lator 3 It is also possible to start the FlashTools via external signals applied to the DB 9 socket P1A This requires control of the signal transition on the Reset line RESIN via pin 7 while a static...

Page 61: ...open Pin 9 of DB 9 socket P1A not connected JP22 open Pin 7 of DB 9 socket P1A not connected 1 2 Reset input of the module can be controlled via RTS signal from a host PC JP23 open Pin 4 of DB 9 sock...

Page 62: ...option especially supports connectivity to analog and digital modems Such modem devices enable global communication of the phyCORE P8xC51Mx2 over the Internet or a direct dial connection On all PHYTE...

Page 63: ...eds the limiting value that can be provided by the phyCORE Development Board LD 5V the voltage at pin 6 will be switched off immediately This prevents damage to the phyCORE Development Board LD 5V as...

Page 64: ...n 7 of the DB 9 socket P1B not connected JP4 open Pin 4 of the DB 9 socket P1B not connected JP5 open Pin 6 of the DB 9 socket P1B not connected JP6 open Pin 8 of the DB 9 socket P1B not connected JP7...

Page 65: ...gs are not functional and could damage the module Jumper Setting Description JP3 closed Pin 7 of the DB 9 socket P1B is connected to SCL I C of the phyCORE P8xC51Mx2 JP6 closed Pin 8 of the DB 9 socke...

Page 66: ...lug P2A not connected with pin 15D of the phyCORE P8xC51Mx2 NC JP11 open Input at optocoupler U4 on the phyCORE Development Board LD 5V open JP12 open Output at optocoupler U5 on the phyCORE Developme...

Page 67: ...ptocoupler U5 on the Development Board connected with NC pin 15D on phyCORE P8xC51Mx2 JP12 2 3 Port P4 1 TxD1 from P8xC51Mx2 is connected to CAN transceiver U2 via optocoupler U5 JP13 1 2 Supply volta...

Page 68: ...8xC51Mx2 JP34 open Pin 7 of DB 9 plug P2B disconnected from signals on the Development Board JP14 open CAN optocoupler U6 on the Development Board disconnected from module pins JP15 open CAN optocoupl...

Page 69: ...ected with NC pin 14D of the phyCORE P8xC51Mx2 2 3 CAN optocoupler U6 connected with port P4 0 on the phyCORE P8xC51Mx2 JP15 1 2 CAN optocoupler U7 connected with NC pin 15D on the phyCORE P8xC51Mx2 2...

Page 70: ...1 0 GPIO0 Control and illumination of the LED can be enabled via user code toggling port pin P1 0 or data bit D0 at address 00 FDA0h IOSW 0 or 3F FDA0h IOSW 1 A low level at port pin P1 0 or latch U14...

Page 71: ...optional expansion board that mounts to the Development Board at X2 Please note that depending on the design and size of the expansion board only a portion of the entire patch field is utilized under...

Page 72: ...scheme for expansion bus connector and patch field matrices differs from that of the phyCORE connector as shown in the following two figures B A D C 80 1 80 1 Figure 23 Pin Assignment Scheme of the E...

Page 73: ...4 AD4 14B 21A 34D P0 5 AD5 14C 21B 34F P0 6 AD6 15A 22B 35A P0 7 AD7 15C 23A 35E A0 6A 8B 30B A1 6B 9A 30D A2 6C 10A 30F A3 7A 10B 31A A4 7C 11A 31E A5 8A 11B 31B A6 8C 12B 31F A7 9A 13A 32A P2 0 A8...

Page 74: ...ignal phyCORE P8xC51Mx2 Expansion Bus Patch Field RESET 6E 10C 3D RESIN 6F 10D 3F WDI 4D 8D 3A BOOT 6D 9C 3B P1 0 T2 7D 11D 4A P1 1 T2EX 8D 12D 4B P1 2 ECI 8F 13C 4F P1 3 CEX0 9D 13D 5A P1 4 CEX1 MOSI...

Page 75: ...2A 47A 52A 57A 62A 67A 72A 77A 4B 9B 14B 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B 3C 7C 12C 17C 22C 27C 32C 37C 42C 47C 52C 57C 62C 67C 72C 77C 3D 9D 14D 19D 24D 29D 34D 42D 47D 52D 57D 62D...

Page 76: ...D 10A to 27A 37A to 54A 10B to 27B 37B to 54B 10C to 27C 37C to 54C 12D to 27D 39D to 54D 10E to 27E 37E to 54E 10F to 27F 36F to 54F except GND pins in row C and D Table 39 Unused Pins on the phyCOR...

Page 77: ...Board LD 5V can be connected to a port pin at GPIO1 JP19 1 2 or the data bus via latch U14 and driver U15 JP19 2 3 When using the phyCORE P8xC51Mx2 the factory default configuration enables access to...

Page 78: ...der Connector X4 The pin header X4 on the Development Board enables connection of an optional modem power supply Connector X4 supplies 5 V at pin 1 and provides the phyCORE Development Board LD 5V GND...

Page 79: ...30 D Default Memory Model 25 Development Board Connectors and Jumpers 52 DS2401 79 E EEPROM Configuration 21 EMC 1 Expansion Bus 72 F Features 5 First Serial Interface 61 Flash Memory 36 Functional Co...

Page 80: ...ternal Devices via Socket P1A 62 PRG EN 27 R RAM SW 28 Real Time Clock 39 Remote Download 23 Remote Supervisory Chip 42 Reset Button 53 Reset Controller 41 RS 232 Interface 33 RS 232 Transceiver 18 19...

Page 81: ...CORE P8xC51Mx2 Document number L 602e_3 April 2005 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Te...

Page 82: ...Published by PHYTEC Messtechnik GmbH 2005 Ordering No L 602e_3 Printed in Germany...

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