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phyCORE Development Board PCM-982

                                                                                                                                                

                                                                                                                                                

 PHYTEC Messtechnik GmbH 2005     L-645e_1

65

10.3.4

 

First CAN Interface at Plug P1A

Plug P1A is the bottom plug of the double DB-9 connector at P1. P1A
is connected to the first CAN interface (CAN_0) of the
phyCORE-MCF548x via jumpers. Depending on the configuration of
the CAN transceivers and their power supply, the following two
configurations are possible:

1.

 

CAN transceiver on the phyCORE-MCF548x is populated and the
CAN signals from the module extend directly to plug P1A.

Jumper

Setting

Description

JP1

1 + 2

Pin 7 of the DB-9 plug P1A is connected to CAN_H0

from on-board transceiver on the phyCORE module

JP2

1 + 2

Pin 2 of the DB-9 plug P1A is connected to CAN_L0

from on-board transceiver on the phyCORE module

Table 14:

Jumper Configuration for CAN Plug P1A Using the CAN
Transceiver on the phyCORE-MCF548x

 

1

 

2

 

3

 

4

 

7

 

6

 

5

 

8

 

9

 

Pin 7 CAN_H0  (non-isolated) 

Pin 2 CAN_L0  (non-isolated) 

Pin 6 CAN_GND 

Pin 3 CAN_GND 

Figure 17:

Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on
phyCORE-MCF548x, Front View)

Summary of Contents for phyCORE-MCF548x

Page 1: ...A product of a PHYTEC Technology Holding company phyCORE MCF548x Hardware Manual Edition January 2005 ...

Page 2: ...C Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2005 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including th...

Page 3: ...DRAM 42 6 3 Serial Memory 43 7 XPLD System Logic Device 45 7 1 XPLD Firmware Development 46 8 Serial Interfaces 47 8 1 RS 232 Interface 47 8 2 CAN Interface 48 8 3 BDM Debug Interface 50 8 4 Ethernet Interface 52 8 4 1 PHY Physical Layer Transceiver 52 8 4 2 MAC Address 54 8 5 USB 2 0 Interface 54 9 Real Time Clock RTC 8564 U16 55 10 phyCORE Development Board PCM 982 57 10 1 Concept of the phyCORE...

Page 4: ...at Plug P1B 67 10 3 6 Programmable LED D29 69 10 3 7 Pin Assignment Summary of the phyCORE the Expansion Bus and the Patch Field 69 10 3 8 Silicon Serial Number Temperature Sensor 78 10 3 9 BDM Port X2 79 10 3 10 Technical Specification of the Development Board 80 10 3 11 Release Notes 82 11 Technical Specifications of the phyCORE MCF548x 83 12 Hints for Handling the Module 86 13 Design Considerat...

Page 5: ...e Development Board PCM 982 60 Figure 12 Numbering of Jumper Pads 61 Figure 13 Location of the Jumpers View of the Component Side 61 Figure 14 Connecting the Supply Voltage at X10 63 Figure 15 Pin Assignment of the DB 9 Socket P2A as First RS 232 Front View 64 Figure 16 Pin Assignment of the DB 9 Socket P2B as Second RS 232 Front View 64 Figure 17 Pin Assignment of the DB 9 Plug P1A CAN Transceive...

Page 6: ...ort 38 Table 5 Choice of Flash Memory Devices and Manufacturers 40 Table 6 DDR SDRAM Device Selection 42 Table 7 Serial Memory Options for U15 43 Table 8 Serial Memory I2 C Address Examples 44 Table 9 26 Pin BDM Connector X1 and Corresponding Pins on the phyCORE Connector X2 51 Table 10 Signal Definition PHY 0 Ethernet Port U17 53 Table 11 Signal Definition PHY 1 Ethernet Port U18 53 Table 12 Sign...

Page 7: ...paration 68 Table 18 Signal Pin Assignment for the phyCORE MCF548x Development Board Expansion Board 76 Table 19 Pin Assignment Power Supply for the phyCORE MCF548x Development Board Expansion Board 77 Table 20 Pin Assignment of the BDM Pin Header X2 79 Table 21 Technical Data of the Development Board PCM 982 81 Table 22 Technical Data of the phyCORE MCF548x 84 ...

Page 8: ...phyCORE MCF548x PHYTEC Messtechnik GmbH 2005 L 645e_1 ...

Page 9: ...he LSB while D31 and A31 represent the MSB These conventions are also valid for the parallel I O signals Declaration regarding Electro Magnetic Conformity of the PHYTEC phyCORE MCF548x PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e for use as a test and prototype platform for hardware software developme...

Page 10: ...uld ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE MCF548x is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports common 8 16 and selected 32 bit controllers on two types of Single Boards Comput...

Page 11: ...imately 20 of all pin header connectors on the phyCORE boards to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packa...

Page 12: ...Computer in subminiature form factor 70 x 57 mm according to phyCORE specifications all applicable controller and other logic signals extend to two high density 160 pin Molex connectors processor Freescale embedded ColdFire MCF548X 200 MHz clock Internal Features of the MCF548X 32 bit ColdFire V4e core 200 MHz CPU speed 32 kByte instruction cache 32 kByte data cache MMU with 32 entries 64 bit FPU ...

Page 13: ...wo 10 100Mbit Ethernet ports Logic Device Lattice ispXPLD 5000 family 256 512 768 Macrocells and 128 256 384 kBit SRAM in system programmable For applications like single dual port RAM or FIFO Timer PWM CapComp etc Decoder Encoder IP core application specific logic special bus interfaces multi purpose I O signals etc PCI 2 2 bus SPI bus Synchronous Serial Interface with two Chip Selects I2 C bus I...

Page 14: ...dar Alarm I 2 C Memory FRAM or EEPROM or SRAM RS232 Transceiver CAN Transceiver CAN Transceiver FlexCAN 0 FlexCAN 1 PSC UART 2 PSC UART 0 MCF5485 50 MHz Quarz p h y C O R E C o n n e c t o r 64 to 128MB DDR SDRAM 200MHz 32 bit XPLD Logic Device Free User Logic and I O RS232 Transceiver PSC UART 1 PSC UART 3 Power Supply UART1 TTL Ethernet PHY 0 Ethernet PHY 1 10 100 Mbit Ethernet 1 FEC FastEtherne...

Page 15: ...U15 U19 J7 U10 J11 J22 J14 J18 J37 U11 J2 J8 U21 J13 J1 U14 J38 J35 J27 U17 U13 J10 J17 U12 J23 J4 J24 J16 ColdFire MCF548x XPLD BDM Flash Flash Phy Pin 1 PCB 1229 0 PHYTEC U9 XT3 Q1 U3 J30 J9 J32 U4 U20 J20 XT1 J25 J33 U23 U18 J29 U8 J26 J31 J34 X1 Pin 2 SDRAM SDRAM Phy X2 1A X2 1B 1C 1D Figure 2 View of the phyCORE MCF548x Revision 1229 0 M 1 5 1 ...

Page 16: ...X2 1C 2C 1D 2D 4D 5D GND X2 3C 3D 7C 9D 12C 14D Caution We recommend connecting all available 3V3 input pins to the power supply system on a custom carrier board housing the phyCORE MCF548x and at least the matching number of GND pins neighboring the 3V3 pins In addition proper implementation of the phyCORE module into a target application also requires connecting all GND pins neighboring signals ...

Page 17: ...res to ensure that the module connections are protected from overloading through connected peripherals As Figure 3 indicates all controller signals extend to surface mount technology SMT connectors 0 635 mm lining two sides of the module referred to as phyCORE connector refer to section 11 This allows the phyCORE MCF548x to be plugged into any target application like a big chip Figure 3 Pinout of ...

Page 18: ...he Freescale MCF548x User Manual Data Sheet for details on the functions and features of controller signals and port pins Pin Number Signal I O Comments Pin Row X1A 1A EXTCLK I Clock input for GCLK3 of the XPLD 10 kOhm pull down 2A 7A 12A 17A 22A 27A 32A 37A 42A 47A 52A 57A 62A 67A 72A 77A GND Ground 0 V 3A IRQ7 I Interrupt input 7 of the ColdFire processor I GPI PIRQ7 Reset state GPI 4A XPLD3_0 I...

Page 19: ...PLD0_1 XPLD0_2 XPLD0_4 XPLD0_7 XPLD0_9 XPLD0_10 XPLD0_12 XPLD0_15 XPLD0_17 XPLD0_18 XPLD GPIO Freely available I O pins to implement application specific functionality 41A FB_CS4 O Chip Select 4 of the ColdFire FlexBus Reset state high I O PFBCS4 GPIO 43A DACK0 O DMA acknowledge 0 I O PDMA2 GPIO Reset state GPI O TOUT0 GP timer output 0 44A DACK1 O DMA acknowledge 1 I O PDMA3 GPIO Reset state GPI ...

Page 20: ...5 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_AD14 PCI_AD12 PCI_AD10 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1 I O PCI address data bus Reset state tristate Bootstrap configuration1 FBMODE 1 Refer to A 1 for additional information O FBADDRx FlexBus address lines 58A PCI_CXBE3 I O PCI command byte enable signal 3 Reset state tristate 64A PCI_CXBE2 I O PCI command byte enable signal 2 Reset state tristate...

Page 21: ... input 5 of the ColdFire processor I GPI PIRQ5 Reset state GPI 3B IRQ6 I Interrupt input 6 of the ColdFire processor I GPI PIRQ6 Reset state GPI 4B 9B 14B 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B GND Ground 0 V 5B FB_CS2 O Chip Select 2 of the ColdFire FlexBus Reset state high I O PFBCS2 GPIO 6B FB_CS3 O Chip Select 3 of the ColdFire FlexBus Reset state high I O PFBCS3 GPIO ...

Page 22: ...19 I O XPLD GPIO Free usable pins to implement application specific functionality 41B FB_CS5 O Chip Select 5 of the ColdFire FlexBus Reset state high I O PFBCS5 GPIO 42B DREQ0 I DMA request signal 0 of the processor I O PDMA0 GPIO Reset state GPI I TIN1 GP timer input 1 43B DREQ1 I DMA request signal 1 of the processor I O PDMA1 GPIO Reset state GPI I TIN0 GP timer input 0 I IRQ1 interrupt input 1...

Page 23: ...1B 62B 63B 70B 71B 72B 73B 76B 77B 78B 80B PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_AD22 PCI_AD20 PCI_AD18 PCI_AD16 PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 I O PCI address data bus Reset state tristate Bootstrap configuration1 FBMODE 1 Refer to A 1 for additional information O FBADDRx FlexBus address lines 58B PCI_IDSEL I PCI initialization device select signal Reset stat...

Page 24: ...XPLD0_20 I O XPLD GPIO Freely available pins to implement application specific functionality 10C RSTI I O Reset input signal of the ColdFire processor Reset signal supplied by the voltage supervision device U23 to the processor s RSTI reset input pin Can be driven externally Input resistance is 1kOhm Do not connect push buttons e g to this pin This pin should be controlled by logic devices only It...

Page 25: ...ta signal I O PPSC1PSC05 GPIO Reset state GPI 20C TXD1_TTL O PSC1 transmit data signal I O PPSC1PSC04 GPIO Reset state GPI 21C RXD1 I RxD input on the RS 232 transceiver for the second ColdFire UART PSC1 23C TXD1 O TxD output on the RS 232 transceiver for the second ColdFire UART PSC1 24C RTS1_TTL I PSC1 request to send signal I O PPSC1PSC06 GPIO Reset state GPI I PSC1FSYNC PSC1 frame sync 25C CTS...

Page 26: ...p configuration MTMOD0 0 I TRST JTAG reset 64C TCK I JTAG test clock input 65C DSO O BDM debug serial output Reset state high Bootstrap configuration MTMOD0 0 TDO JTAG data output 66C 68C 69C PSTDDATA6 PSTDDATA4 PSTDDATA2 O ColdFire processor status debug data output 70C TA I Transfer acknowledge on the FlexBus Reset state tristate I O PFBCTL1 GPIO PAR_TA 0 71C PSTCLK O Processor clock output Supp...

Page 27: ...23 XPLD0_21 I O XPLD GPIO Freely available pins to implement application specific functionality 10D RESIN I Manual reset input of the voltage supervisor device U23 Asserting RESIN results in asserting the system reset RSTI After negation of RESIN the system reset RSTI stays active for additional 200ms reset delay This signal can be used for connection of a reset push button e g Signal connected to...

Page 28: ...interface Jumper J13 must be closed to use this interface 23D TXD0 O TxD output on the RS 232 transceiver for the first serial interface 25D RTS0_TTL I PSC0 request to send signal I O PPSC1PSC02 GPIO Reset state GPI I PSC0FSYNC PSC0 frame sync 26D CTS0_TTL O PCS0 clear to send signal I O PPSC1PSC03 GPIO Reset state GPI I PSC0BCLK PSC0 modem clock 27D DSPI_SIN I DSPI serial data in signal I O PDSPI...

Page 29: ... interrupt request input 3 I CANRX1 FlexCAN receive input 1 47D TOUT3 I GP timer 3 output I O PTIM6 GPIO Reset state GPI O CANTX1 FlexCAN transmit output 1 66D 67D 68D 70D 71D PSTDDATA7 PSTDDATA5 PSTDDATA3 PSTDDATA1 PSTDDATA0 O ColdFire processor status debug data output 72D XPLD_TDI I XPLD JTAG data input 73D XPLD_TDO O XPLD JTAG data output 75D 76D 77D 78D ADC7 ADC5 ADC4 ADC2 I Analog input of t...

Page 30: ...phyCORE MCF548x 22 PHYTEC Messtechnik GmbH 2005 L 645e_1 ...

Page 31: ...the location of the jumpers on the board 1 2 3 1 2 3 4 6 7 8 9 1 2 1 2 open closed 1 2 3 4 5 6 Figure 4 Numbering of the Jumper Pads OZ1 J15 J5 J6 J36 U7 XT2 J19 U6 U22 J3 U16 X1 U1 U5 J21 J28 J12 U15 U19 J7 U10 J11 J22 J14 J18 J37 U11 J2 J8 U21 J13 J1 U14 J38 J35 J27 U17 U13 J10 J17 U12 J23 J4 J24 J16 ColdFire MCF548x XPLD BDM Flash Flash Phy Pin 1 PCB 1229 0 PHYTEC Figure 5 Location of the Jumpe...

Page 32: ...GmbH 2005 L 645e_1 U9 XT3 Q1 U3 J30 J9 J32 U4 U20 J20 XT1 J25 J33 U23 U18 J29 U8 J26 J31 J34 X1 Pin 2 SDRAM SDRAM Phy X2 1A X2 1B 1C 1D z Figure 6 Location of the Jumpers Connector Side and Default Settings phyCORE MCF548x Standard Version ...

Page 33: ...ut signal The processor s CAN output must be configured by software Please refer to the Processor User s Manual for more detailed information 1 2 Connects E1_MDC to CANTX0 2 3 X Connects RTS2_TTL to CANTX0 Package Type 0R in SMD 0402 J4 CANRX0 signal selection Software has to initialize this signal routing for the FLEX CAN signals 1 2 Connects E1_MDIO to CANRX0 2 3 X Connects CTS2_TTL to CANRX0 Pa...

Page 34: ...upt to the IRQ1 DREQ1 input on the processor 2 3 Connects the PHY interrupt to the IRQ2 TIN2 input on the processor Package Type 0R in SMD 0402 J9 Connection of the interrupt output E1_INT on the PHY at U18 to the processor 1 2 X Connects the PHY interrupt to the IRQ4 PCI_BR4 input on the processor 2 3 Connects the PHY interrupt to the IRQ3 TIN3 input on the processor Package Type 0R in SMD 0402 J...

Page 35: ...pulating the phyCORE MCF548x will have this writing protection function Please refer to the corresponding memory data sheet for more detailed information open X closed Package Type 0R in SMD 0402 J15 J15 connects the CANTX1 input of the CAN transceiver U11 to the desired processor CAN output signal The processor s CAN output must be configured by software Please refer to the Processor User s Manua...

Page 36: ...R in SMD 0402 J19 J20 FXSD FXEN pin configuration for Ethernet PHY U17 U18 Refer to the Micrel KS8721B BT data sheet for details 1 2 Enable Fiber mode connects FXSD FXEN to 2V5 2 3 X Disable Fiber mode connects FXSD FXEN to GND Package Type 0R in SMD 0402 J21 J21 allows for alternate CAN signal routing of the FlexCAN 0 interface This jumper must only be closed if no CAN transceiver populates U10 o...

Page 37: ... 2 3 A2 0 A1 1 A0 0 0xA4 0xA5 2 3 1 2 A2 1 A1 1 A0 0 0xAC 0xAD Package Type 0R in SMD 0402 J25 J25 selects the I O voltage for the XPLD VCCO0 VCCO0 supplies the XPLD signals XPLD0_0 to XPLD0_35 VCCO1 and VCCO2 of the XPLD are connected to 3V3 1 2 X I O voltage 3V3 3 4 I O voltage 2V5 5 6 I O voltage 1V5 Package Type 0R in SMD 0805 J26 J26 selects the I O voltage for the XPLD VCCO3 VCCO3 supplies t...

Page 38: ...FB_BWE3 is connected to XPLD0_19 Package Type 0R in SMD 0402 J31 J31 connects the power down control input E0_PD of the Ethernet 0 PHY transceiver U17 to the XPLD signal XPLD0_32 E0_PD has a pull up resistor of 10kOhm open X E0_PD is not connected to XPLD0_32 closed E0_PD is connected to XPLD0_32 Package Type 0R in SMD 0402 J32 J32 connects the power down control input E1_PD of the Ethernet 1 PHY ...

Page 39: ...sed XPLD_CLK2 is connected to XPLD0_34 Package Type 0R in SMD 0402 J35 J35 connects the digital ground to the analog ground open GND is not connected to GNDA closed X GND is connected to GNDA Package Type 0R in SMD 0805 J36 J36 selects the VCAN power supply for the CAN transceivers at U10 and U11 depending on the devices populating the module 1 2 X VCAN is connected to 3V3 2 3 VCAN is connected to...

Page 40: ...phyCORE MCF548x 32 PHYTEC Messtechnik GmbH 2005 L 645e_1 ...

Page 41: ... CAN transceivers populating U10 and U11 VIN5V is connected to the applicable supply pin on these devices by closing Jumper J36 at position 2 3 The standard version of the phyCORE module uses Texas Instruments SN65HVD230 CAN transceivers that are supplied with 3V3 J36 1 2 VBAT is the input pin that supplies the internal power down voltage VPD VBAT is connected over two schottky diodes D10 and D11 ...

Page 42: ...generated voltages 1V5 2V5 3V3 1V5 ColdFire Core 2V5 DDR SDRAM and Ethernet PHY 3V3 ColdFire I O Flash memory and XPLD VBAT 3V VPD 3V3 I2 C Bus RTC U16 I2 C Bus Memory U15 FlexCAN 0 Transceiver U10 FlexCAN 1 Transceiver U11 VIN5V VCAN Solder Jumper J7 Solder Jumper J36 Power DC DC Converter 2V5 1V5 ...

Page 43: ...lue the supervisor chip adds an additional 200 ms delay until the RSTI line will be inactive high RSTI connects to the processor reset input RSTI is a bi directional signal that can be connected to more then one source For instance RSTI is also connected to the BDM connector of the phyCORE module The resistance of the signal is 1kOhm Special care must be taken when using this signal externally Do ...

Page 44: ...phyCORE MCF548x 36 PHYTEC Messtechnik GmbH 2005 L 645e_1 ...

Page 45: ...mory configuration BDM JTAG configuration The following default configuration is read by the processor with the rising edge of reset line RSTI FlexBus Line Logic Level Description Default FB_AD0 FB_AD1 0 0 PSCONFIG Port Size Configuration of FB_CS0 connected to Boot Flash Memory 32 bit port FB_AD2 1 AACONFIG Auto Acknowledge Configuration for FB_CS0 63 wait states enabled FB_AD3 1 BECONFIG Byte En...

Page 46: ...Logic Level Description Default MTMOD3 MTMOD2 MTMOD1 reserved Each line tied to GND over 4k7 resistor MTMOD0 0 Determines the signal assignment of the test debug port lines MTMOD0 1 select JTAG mode MTMOD0 0 selects BDM mode BDM mode Table 4 System Start up Configuration Test Debug Port MTMOD0 should not be changed while RSTI is inactive high Dynamic switching between BDM and JTAG operation is not...

Page 47: ...Byte to 32 kByte serial memory EEPROM FRAM buffered SRAM The Flash memory is connected to the ColdFire FlexBus and is controlled by FB_CS0 This Chip Select signal is used for boot operation The DDR SDRAM is connected to the special SDRAM interface of the Freescale ColdFire processor and operates at the maximum frequency Communication to the small non volatile memory device EPROM FRAM or SRAM is es...

Page 48: ...32 MByte Intel 0x8801 0x0089 28F128K3 16 MByte Intel 0x8802 0x0089 28F640K3 8 MByte Intel 0x8803 0x0089 Asynchronous Devices 28F256J3 32 MByte Intel 0x001D 0x0089 28F128J3 16 MByte Intel 0x0018 0x0089 28F640J3 8 MByte Intel 0x0017 0x0089 28F320J3 4 MByte Intel 0x0016 0x0089 Table 5 Choice of Flash Memory Devices and Manufacturers1 The organization of the Flash memory bank is 32 bit Two of these 16...

Page 49: ... to 40 ns The access time can be extended with the software configurable wait states One wait state adds a clock cycle time of 20 ns To support all memory speed grades up to 120 ns an access cycle time of 120 ns should be configured This means that at least 4 wait states must be added for FB_CS0 4 wait states for FB_CS0 supports all possible module configurations Following reset a synchronous Flas...

Page 50: ...f 200 MHz The DDR SDRAM memory bank consist of two devices with 16 bit port size each in parallel to support the 32 bit bus width of the processor The memory bank is controlled by Chip Select signal SD_CS0 of the processor s DDR SDRAM controller Table 6 shows all possible memory configurations Available Capacity Device Organization Devices two 32 MByte 128 MBit 2 MBit x 16 x 4 Banks MT46V8M16 TSOP...

Page 51: ...requency Address Pins Write Cycles Life of Data Device Manufacturer 256 512 Byte 400 kHz A2 A1 A0 1 000 000 100 yrs CAT24WC02 04 CATALYST 1 2 kByte 400 kHz A2 A1 A0 1 000 000 100 yrs CAT24WC08 16 CATALYST 4 8 kByte 400 kHz A2 A1 A0 1 000 000 100 yrs CAT24WC32 64 CATALYST EEPROM 32 kByte 1 MHz A1 A0 100 000 100 yrs CAT24WC256 CATALYST 512 Byte 1 MHz A2 A1 10 billion 10 yrs FM24C04 RAMTRON FRAM 8 kB...

Page 52: ...Address J23 A1 J24 A2 0xA0 0xA1 1 2 2 3 0xA4 0xA5 2 3 2 3 0xA8 0xA9 1 2 1 2 0xAC 0xAD 2 3 1 2 Table 8 Serial Memory I2 C Address Examples Address lines A1 and A2 are not always made available with certain serial memory types This should be noted when configuring the I2 C bus slave address R W Serial Memory I2 C Address A0 A1 A2 0 1 0 1 J24 J23 GND 0xA ...

Page 53: ... XPLD during runtime of the processor via the JTAG port The XPLD JTAG port can served by an external source programming cable e g or by the on board ColdFire processor over general purpose I O pins The XPLD is a member of the ispXPLD 5000MX family provided by Lattice Semiconductor www latticesemi com Lattice ispXPLD LC5256MV 5F256 75I Device Features 256 Macrocells 128 kBit internal memory for sin...

Page 54: ...attice Semiconductor The tool can be downloaded from www latticesemi com and is free in its basic version This version is suitable to compile and create the programmable output file ColdFire MCF548x XPLD Logic Device 256 to 768 Macrocells SuperWIDE Logic Arithmetic capability 300 MHz speed very flexible signal routing FlexBus FB_AD 31 0 Control Signal 50MHzClock 128 to 384kBit Single or Dual port ...

Page 55: ...micrcontroller s on chip UART supports handshake signal communication Use of an RS 232 signal level in support of handshake communication requires use of an external RS 232 transceiver not located on the module Furthermore it is possible to use the TTL signals of both of the UART channels externally These signals are available at X2D16 X2D17 RXD0_TTL TXD0_TTL and X2C19 X2C20 RXD1_TTL TXD1_TTL on t...

Page 56: ...lvanic isolation of the CAN signals is required For larger CAN bus systems an external opto coupler should be implemented to galvanically separate the CAN transceiver and the phyCORE MCF548x To add external circuits for optical isolation the CAN transceivers must be removed and the CAN bus signals bypassed by means of soldering jumpers J21 and J22 Then the CAN TTL signals are routed to pins X2C18 ...

Page 57: ... Configuration of the On Board Transceiver The transceivers at U10 and U11 can be switched to stand by by populating jumpers J17 and J18 with a 10k resistor position 2 3 Furthermore the signal rise time can be configured by closing both jumpers at 1 2 leaving 2 3 open This results in reduced interference from the CAN bus when using lower baud rates For additional information refer to the data shee...

Page 58: ...atures internal breakpoint registers enabling debugging in Flash memory The on chip BDM interface extends from the MCF548X to a 26 pin connector at which an external BDM signal converter circuitry can be attached Such BDM signal converters enable connection of the MCF548X to a host PC for debugging purposes This BDM converter is NOT located on the phyCORE MCF548x module The BDM signals are availab...

Page 59: ...n a Development Board to a host PC for start up download of user code and debugging Table 9 shows the pin assignment on the 26 pin BDM header X1 BDM Pin Signal1 BDM Header X1 phyCORE X2 1 reserved not connected 2 BKPT BKPT D63 3 GND GND C62 4 DSCLK DSCLK C63 5 GND GND D64 6 reserved TCK C64 7 RSTI RSTI C10 8 DSI DSI D65 9 3V3 VDDIO 3V3 C1 D1 C2 D2 D4 D5 10 DSO DSO C65 11 GND GND C67 12 PSTDDATA7 P...

Page 60: ... in 10Base T and 100Base T networks The 10 100Base T interface with its LED monitoring signals extends to phyCORE connector X2 The MII interface of the FEC s is not available to the user In order to connect the module to an existing 10 100Base T network some external circuitry is required It is important to note that the Physical Layer Transceiver KS8721B MICREL www micrel com implemented on the p...

Page 61: ...oggle activity C33 E0_LED1 Speed LED output H LED off 10BT L LED on 100BT C34 Table 10 Signal Definition PHY 0 Ethernet Port U17 Table 11 shows the interface signals for the Ethernet channel 1 FEC Channel 1 PHY U18 Pin Function phyCORE Connector X2 E1_RX Differential positive receive input signal D40 E1_RX Differential negative receive input signal C40 E1_TX Differential positive transmit output s...

Page 62: ... 12 position HEX value 8 5 USB 2 0 Interface The phyCORE MCF548x integrates a complete USB 2 0 compliant slave interface This interface supports high speed 480 Mbit s and full speed 12 Mbit s transmission rates The USB 2 0 controller is integrated in the ColdFire processor including the physical layer transceiver unit Table 12 shows the USB signals extend to the phyCORE module connector X2 USB 2 0...

Page 63: ...a battery VBAT the Real Time Clock runs independently of the board s power supply The Real Time Clock is programmed via the I2 C bus address 0xA2 0xA3 Since the MCF548X is equipped with an internal I2 C controller the I2 C protocol is processed very effective without extensive processor action refer also to section 6 3 The Real Time Clock also provides an interrupt output that extends to the WAKEU...

Page 64: ...ore information on the features of the RTC 8564 refer to the corresponding Data Sheet Note After connection of the supply voltage or after a reset the Real Time Clock generates no interrupt The RTC must first be initialized see RTC Data Sheet for more information ...

Page 65: ... in laboratory environments prior to their use in customer designed applications 10 1 Concept of the phyCORE Development Board PCM 982 The phyCORE Development Board PCM 982 provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyCORE MCF548x Single Board Computer module The Development Board design allows easy con nection of additional expansi...

Page 66: ...USB host sockets X7 dual USB host sockets X8 Compact Flash card socket X9 MMC SD card socket X10 socket for 5 volt power supply connectivity X11 pin header 2 54 mm for 12 V 12 V power supply to the PCI slot X12 mating receptacle for expansion board connectivity X13 housing shielding contact J2 USB slave MCF socket L16 LAN port 0 10 100 Mbit s Ethernet RJ 45 socket L17 LAN port 1 10 100 Mbit s Ethe...

Page 67: ...V D32 green power LED monitors 3V3 D33 red LED monitors the RSTI line Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate s...

Page 68: ... 645e_1 CF Card MMC SD Card BDM Port Dual FlexCAN Dual RS232 Boot Reset Single USB 2 0 Slave Port Quad USB 2 0 Host Port LAN 0 10 100 MBit PCI Slot Expansion Bus Expansion Bus 5V Power LAN 1 10 100 MBit Figure 11 View of the Development Board PCM 982 ...

Page 69: ...no jumpers are set no signals are connected to the CAN transceivers The reset input on the phyCORE MCF548x directly connects to the Reset button S2 Figure 12 illustrates the numbering of the jumper pads while Figure 13 indicates the location of the jumpers on the Development Board with its default configuration Figure 12 Numbering of Jumper Pads CF Card MMC SD Card BDM Port Dual FlexCAN Dual RS232...

Page 70: ... CAN_H1 signal 1 2 X Connects CAN_H1 to pin 7 of P1B 1 3 Connects CAN_H1 to the opto coupler U8 2 4 Connects transceiver output CAN_H1_TR to P1B JP4 Routing of the CAN_L1 signal 1 2 X Connects CAN_L1 to pin 2 of P1B 1 3 Connects CAN_L1 to the opto coupler U12 2 4 Connects transceiver output CAN_L1_TR to P1B Table 13 Development Board Jumper Overview Figure 13 shows the factory default jumper setti...

Page 71: ...ORE Development Board PCM 982 depending on user needs 10 3 1 Power Supply at X10 Caution Do not use a laboratory adapter to supply power to the Development Board Power spikes during power on could destroy the phyCORE module mounted on the Development Board Do not change modules or jumper settings while the Development Board is supplied with power Permissible input voltage 5 VDC 10 regulated The re...

Page 72: ...t utilizes the on board RS 232 transceivers for the first serial interface 1 2 3 4 7 6 5 8 9 Pin 2 TXD0 Pin 3 RXD0 Pin 5 GND Figure 15 Pin Assignment of the DB 9 Socket P2A as First RS 232 Front View 10 3 3 Second Serial Interface at Socket P2B Socket P2B is the top socket of the double DB 9 connector at P2 1 2 3 4 7 6 5 8 9 Pin 2 TXD1 Pin 3 RXD1 Pin 5 GND Figure 16 Pin Assignment of the DB 9 Sock...

Page 73: ...yCORE MCF548x is populated and the CAN signals from the module extend directly to plug P1A Jumper Setting Description JP1 1 2 Pin 7 of the DB 9 plug P1A is connected to CAN_H0 from on board transceiver on the phyCORE module JP2 1 2 Pin 2 of the DB 9 plug P1A is connected to CAN_L0 from on board transceiver on the phyCORE module Table 14 Jumper Configuration for CAN Plug P1A Using the CAN Transceiv...

Page 74: ...N_H0 CAN_TX of the phyCORE MCF548x JP2 2 4 1 31 Pin 2 of the DB 9 plug P1A is connected to CAN_L0 from on board transceiver on the Development Board PCM 982 Output at opto coupler U7 on the phyCORE Development Board PCM 982 connected with CAN_L0 CAN_RX of the phyCORE MCF548x Table 15 Jumper Configuration for CAN Plug P1A Using the CAN Transceiver on the Development Board with Galvanic Separation 1...

Page 75: ... phyCORE MCF548x is populated and the CAN signals from the module extend directly to plug P1B Jumper Setting Description JP3 1 2 Pin 7 of the DB 9 plug P1B is connected to CAN_H1 from on board transceiver on the phyCORE module JP4 1 2 Pin 2 of the DB 9 plug P1B is connected to CAN_L1 from on board transceiver on the phyCORE module Table 16 Jumper Configuration for CAN Plug P2B Using the CAN Transc...

Page 76: ...N_H1 CAN_TX of the phyCORE MCF548x JP4 2 4 1 31 Pin 2 of the DB 9 plug P1B is connected to CAN_L1 from on board transceiver on the Development Board PCM 982 Output at opto coupler U12 on the phyCORE Development Board PCM 982 connected with CAN_L1 CAN_RX of the phyCORE MCF548x Table 17 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Development Board with Galvanic Separation ...

Page 77: ... expansion bus connector X12 on the Development Board These signals in turn are routed in a similar manner to the patch field on an optional expansion board that mounts to the Development Board at X12 Please note that depending on the design and size of the expansion board only a portion of the entire patch field is utilized under certain circumstances When this is the case certain signals describ...

Page 78: ...g scheme for expansion bus connector an patch field matrices differs from that of the phyCORE connector as shown in the following two figures B A D C 80 1 80 1 Figure 21 Pin Assignment Scheme of the Expansion Bus AB C D E F 54 1 Figure 22 Pin Assignment Scheme of the Patch Field ...

Page 79: ...LD3_16 CF_VS1 33A BUS24 18A XPLD3_19 18A XPLD3_19 CF_IORD 33B BUS27 19A XPLD3_21 19A XPLD3_21 D1 34A BUS29 20A XPLD3_22 20A XPLD3_22 D2 34E BUS30 21A XPLD3_24 21A XPLD3_24 D4 34D BUS32 23A XPLD3_27 23A XPLD3_27 D7 35E BUS35 24A XPLD3_29 24A XPLD3_29 CF_INTRQ 35D BUS37 25A XPLD3_30 25A XPLD3_30 CF_REG 35F BUS38 26A XPLD3_32 26A XPLD3_32 CF_WP 36E BUS40 28A XPLD3_35 28A XPLD3_35 CF_INPK 37A BUS43 29...

Page 80: ...109 70A PCI_CXBE1 70A PCI_CXBE1 50F BUS110 71A PCI_AD14 71A PCI_AD14 51E BUS112 73A PCI_AD12 73A PCI_AD12 52A BUS115 74A PCI_AD10 74A PCI_AD10 52E BUS117 75A PCI_AD8 75A PCI_AD8 52B BUS118 76A PCI_AD7 76A PCI_AD7 53A BUS120 78A PCI_AD5 78A PCI_AD5 53B BUS123 79A PCI_AD3 79A PCI_AD3 54A BUS125 80A PCI_AD1 80A PCI_AD1 54E BUS126 1B CLK_EXT 1B CLK_EXT 28C BUS1 2B IRQ5 2B IRQ5 28E BUS2 3B IRQ6 3B IRQ6...

Page 81: ... CLK_PCI 45B CLK_PCI_EXP 42F BUS71 46B GND 46B GND 43C BUS73 47B PCI_BG0 47B PCI_BG0 43E BUS74 48B PCI_BG1 48B PCI_BG1 43F BUS76 50B PCI_BG2 50B PCI_BG2 44B BUS79 51B PCI_BG3 51B PCI_BG3 44F BUS81 52B PCI_BG4 52B PCI_BG4 45A BUS82 53B PCI_AD30 53B PCI_AD30 45B BUS84 55B PCI_AD28 55B PCI_AD28 46A BUS87 56B PCI_AD26 56B PCI_AD26 46B BUS89 57B PCI_AD24 57B PCI_AD24 46F BUS90 58B PCI_IDSEL 58B PCI_IDS...

Page 82: ...XPLD1_4 9A GPIO23 28C DSPI_CS5 28C DSPI_CS5 9F GPIO26 29C DSPI_CS3 29C DSPI_CS3 10C GPIO28 30C DSPI_CS2 30C DSPI_CS2 10E GPIO29 31C SCL 31C SCL 10F GPIO31 33C E0_LED0 33C E0_LED0 11E GPIO34 34C E0_LED1 34C E0_LED1 11F GPIO36 35C E0_RX 35C E0_RX 12A GPIO37 36C E0_TX 36C E0_TX 12B GPIO39 38C USBVBUS 38C USBVBUS 13A GPIO42 39C E1_LED0 39C E1_LED0 13B GPIO44 40C E1_RX 40C E1_RX 13D GPIO45 41C E1_TX 41...

Page 83: ...DC0 80C ADC0 27A GPIO109 6D VPD 6D VPD 2D VPD 7D XPLD1_0 7D XPLD1_0 2F PFI 8D XPLD1_1 8D XPLD1_1 3A WDI 10D RESIN 10D RESIN 3F RESIN 11D TXD2_TTL 11D TXD2_TTL 4A GPIO0 12D RXD2_TTL 12D RXD2_TTL 4B GPIO1 13D CTS2_TTL 13D CTS2_TTL 5A GPIO3 15D RTS2_TTL 15D RTS2_TTL 5B GPIO6 16D RXD0_TTL 16D RXD0_TTL 6A GPIO8 17D TXD0_TTL 17D TXD0_TTL 6C GPIO9 18D CAN_L1 18D CAN_L1 6B GPIO11 20D CAN_L0 20D CAN_L0 7E ...

Page 84: ...18F GPIO70 56D XPLD0_28 56D XPLD0_28 19E GPIO72 57D XPLD0_27 57D XPLD0_27 19B GPIO73 58D XPLD0_25 58D XPLD0_25 20A GPIO75 60D XPLD0_23 60D XPLD0_23 20B GPIO78 61D XPLD0_21 61D XPLD0_21 21A GPIO80 62D MTMOD0 62D MTMOD0 21C GPIO81 63D BKPT 63D BKPT 21B GPIO83 65D DSI 65D DSI 22E GPIO86 66D PSTDDATA7 66D PSTDDATA7 22D GPIO88 67D PSTDDATA5 67D PSTDDATA5 22F GPIO89 68D PSTDDATA3 68D PSTDDATA3 23E GPIO9...

Page 85: ... 14D 19D 24D 29D 34D 39D 44D 49D 54D 59D 64D 69D GND 2A 7A 12A 17A 22A 27A 32A 37A 42A 47A 52A 57A 62A 67A 72A 77A 4B 9B 14B 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B 3C 7C 12C 17C 22C 27C 32C 37C 42C 47C 52C 57C 62C 67C 72C 3D 9D 14D 19D 24D 29D 34D 39D 44D 49D 54D 59D 64D 69D GNDA 77C 74D 79D GNDA 77C 74D 79D GND 3C 4C 7C 8C 9C 12C 13C 14C 17C 18C 19C 22C 23C 24C 27C 29C 30C 31C 34C 35...

Page 86: ...as copy protection in networked applications The DS18B20 measures the ambient temperature form 55 C to 125 C The accuracy is 0 5 C within 10 to 85 C The device can be soldered at space U15 on the Development Board The Silicon Serial Number Chip mounted on the phyCORE Development Board PCM 982 is connected to port pin XPLD1_4 of the XPLD Figure 23 Connecting the DS18B20 Temperature Sensor with Sili...

Page 87: ... interface BDM Pin Number BDM Header X2 1 Not connected 2 BKPT 3 GND 4 DSCLK 5 GND 6 TCK 7 RSTI 8 DSI 9 3V3 10 DSO 11 GND 12 PSTDDATA7 13 PSTDDATA6 14 PSTDDATA5 15 PSTDDATA4 16 PSTDDATA3 17 PSTDDATA2 18 PSTDDATA1 19 PSTDDATA0 20 GND 21 Not connected 22 Not connected 23 GND 24 PSTCLK 25 1V5 26 TA Table 20 Pin Assignment of the BDM Pin Header X2 Caution Do not install or remove the BDM cable from th...

Page 88: ...phyCORE MCF548x 80 PHYTEC Messtechnik GmbH 2005 L 645e_1 10 3 10 Technical Specification of the Development Board Figure 25 Physical Dimensions of the Development Board PCM 982 ...

Page 89: ...Approximately 190 grams Humidity Max 95 r F not condensed Storage Temp Range 40 to 90 C Operating Temp Range 0 C to 70 C Operating voltages 5 V 10 Operating Power Consumption Voltage 5 V phyCORE MCF548x ColdFire MCF5485 200 MHz core clock 128 Mbyte DDR SDRAM 32 Mbyte Flash without any installed I O line or CF card MMC SD card PCI card or expansion board Typ 750 mA Table 21 Technical Data of the De...

Page 90: ...clusively describes the board revision 4132 0 Revision PCB 4132 0 RESTI signal monitoring LED D33 without function Current limiting resistor R122 is removed With installed R122 RSTI signal don t reach signal low level CF Card socket X8 pin 7 is disconnected from FB_CS1 and wired to the phyCORE connector X1A6 signal XPLD3_1 Power Connector X10 Pins 2 and 3 have to short circuit to connect the syste...

Page 91: ... The physical dimensions of the phyCORE MCF548x are represented in Figure 26 OZ1 U7 XT2 U6 U22 U16 X1 U1 U5 U15 U19 U10 U11 U21 U14 U17 U13 U12 ColdFire MCF548x XPLD BDM Flash Flash Phy Pin 1 PCB 1229 0 PHYTEC U9 XT3 Q1 U3 U4 U20 XT1 U23 U18 U8 X1 Pin 2 SDRAM SDRAM Phy X2 1A X2 1B 1C 1D Figure 26 Physical Dimensions ...

Page 92: ...y installed no BDM header at X1 Approximately 31 grams Humidity Max 95 r F not condensed Storage Temp Range 40 to 90 C Operating Temp Range 40 C to 85 C Operating voltages Voltage 3V3 Optional Voltage VIN5V VBAT 3 3 V 10 5 V 10 Typ 3 V Operating Power Consumption Voltage 3V3 Voltage VBAT 50 MHz input frequency ColdFire MCF5485 200 MHz core clock 128 MByte DDR SDRAM 32 MByte Flash without applied 3...

Page 93: ...the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 3 mm on the underside of the phyCORE must be subtracted Component height 6 mm Manufacturer Molex Number of pins per contact row 160 2 rows of 80 pins each Molex part number 55091 1609 plug Molex part number lead free 55091 1679 plug PHYTEC type number VB082 Component height 10 mm...

Page 94: ...ections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Integrating the phyCORE MCF548x in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module It is recommended that the target applicati...

Page 95: ...ne D0 represents the LSB and D31 the MSB Address line A0 represents the LSB and A31 the MSB Byte ordering is Big Endian Never connect signals to the MCF548X output drivers carrying a higher potential e g pull ups than the internal supply voltage For more information on the controller s I O voltage range as well as other controller related features please refer to the detailed MCF548X User s Manual...

Page 96: ...hyCORE MCF548x 88 PHYTEC Messtechnik GmbH 2005 L 645e_1 14 Revision History Date Version numbers Changes in this manual 1 21 05 Manual L 645e_1 PCM 024 PCB 1229 0 PCM 982 PCB 4132 0 First release version ...

Page 97: ... Messtechnik GmbH 2005 L 645e_1 89 15 Component Placement Diagram INSERT 1229 0BS TurboCAD dxf Figure 27 phyCORE MCF548x Component Placement Top View INSERT 1229 0LS TurboCAD dxf Figure 28 phyCORE MCF548x Component Placement Bottom View ...

Page 98: ...rocessor bug RSTO does not follow RSTI During RSTI active RSTO is held tristate by the processor resulting in a signal level depending on the external connected components RSTO needs an external pull up resistor Bootstrapping option FBMODE is set to FlexBus address bus on PCIAD pins This is done by the pull down resistor R11 Next revision will have a pull up resistor to initiate the PCI bus PCI bu...

Page 99: ...olation 52 Terminating Resistor 54 CAN Bus 52 CAN Connector 64 CAN Interface 52 CAN Transceiver 30 52 CAN_0 72 CAN_1 74 CAN_H 54 CAN_L 54 Concept of the Development Board 63 Connectors 64 CPU Speed 4 D D10 66 D11 66 D12 66 D13 66 D14 66 D15 66 D2 66 D29 66 76 D3 66 D30 66 D31 66 D32 66 D33 66 D4 66 D5 66 D6 66 D7 66 DAC 12 bit 6 DDR SDRAM 6 42 45 Design Considerations 94 Development Board Overview...

Page 100: ...nctional Components on the phyCORE Development Board 70 G GND Connection 93 GND1 64 H Hints for Handling the Module 93 I I C 4 I2 C Bus 31 I2 C Bus Frequency 46 I2 C Interface 46 Intel Strata Flash 43 Introduction 3 ispXPLD LC5256MV 49 J J1 27 J10 28 J11 28 J12 29 J13 29 J14 29 J15 29 J16 29 J17 30 54 J18 30 54 J19 30 J2 27 64 J20 30 J21 30 J22 30 J23 31 46 J24 31 46 J25 31 J26 31 61 J27 31 J28 32...

Page 101: ...70 Internal SRAM2 28 Programmable LED 76 R Real Time Clock 61 Reset 37 Reset Button 68 RS 232 TTL Signals 29 RS 232 Connector 64 RS 232 Interface 51 RTC 46 61 RTC Interrupt 61 S S1 65 S2 65 SDRAM 45 SDRAM Interface 45 Second CAN Interface 74 Second Serial Interface 71 Serial Interfaces 51 Serial Memory 42 46 Silicon Serial Number 85 SMT Connector 11 SN65HV230 52 Socket P2A First RS 232 71 Socket P...

Page 102: ...RT 4 51 USB Full Speed 59 High Speed 59 USB 2 0 59 USB 2 0 Interface 59 USB Slave 59 USB2 0 4 V VB082 92 VB085 92 VBAT 35 VHLD 50 VIN5V 35 Voltage Supervisor 37 VPD 35 46 W Wait State 44 X X1 56 64 X10 64 X11 64 X12 64 78 X13 64 X2 64 X3 64 X4 64 X5 64 X6 64 X7 64 X8 64 X9 64 XPLD 49 XPLD Firmware 50 XPLD System Logic Device 49 ...

Page 103: ...yCORE MCF548x Document number L 645e_1 January 2005 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 ...

Page 104: ...Published by PHYTEC Messtechnik GmbH 2005 Ordering No L 645e_1 Printed in Germany ...

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