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System Description
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1.4 Detailed Description of the UniPhyer LB-UA2348
1.4.1 Module Functional Block Diagram
Figure 0-3 UniPhyer LB-UA2348 Module Functional Block Diagram
The Power Management and PWS Module provide the power and signaling on the Line Ports for the
PhyAdapters. The ADSL module aggregates 24/48 ports signaling traffic into the network processor
card, the network processor terminates the ATM traffic into Ethernet packets through its SAR
(Segmentation and Reassembly) function. The network processor also provides the Layer-2 Ethernet
functions; it can support the mapping between the ATM VCI and VLAN ID (802.1q) and priority
queues (802.1p). The mapping functionality between ATM PVC and VLAN ID include one PVC to
one VLAN ID and multiple PVCs to one VLAN ID; all of which are configurable.
Through the two GBE uplink interfaces, the system can provide Link Aggregation (802.3ad), VLAN
stacking, and Rapid Spanning Tree (802.1w) as ring protection architecture.
Summary of Contents for UniPhyer LB-UA2324
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