10-10
10-10
24
34
44
14
24
VSS
VSS
NC
NC
NC
Flash
EPROM
GND
#
For ROM version: TMS320D16078PGE (MP3-CD-2002)
For ROM version: TMS320D1608xPGE (MP3-CD03)
For Flash version: TMS320DA150PGE160
GND
CD10_SDA
GND
uP_DATA
.... only for ROM version
CD10_RESET
74
74
74
74
IIS_SCLK
# .... only for FLASH version
EEPROM
ADJ
LM317D
uP_CLK
DSP
GND
34
34
34
34
34
34
34
34
34
44
44
44
54
64
64
74
74
74
74
74
74
74
74
74
CD10_SICL
AU_IIS_DATA
IIS_WCLK
CD_IIS_DATA
WE
OE
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
SPDIF_GND
provisional
*
*
*
16.93MHz
+5V
24
24
24
24
24
24
24
24
24
24
24
24
24
34
34
34
34
34
34
34
34
34
34
34
34
34
CD10_RAB
CD10_SILD
Voltage stabilisation
34
34
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SPDIF_GND
600R
for 5V front uP
SPDIF
24
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
24
24
24
24
24
24
24
24
SPDIF
for CD Text version only
+3.3V
SPDIF_GND
only for FLASH version
uP_FRAME
STATUS
GND
CD18_SDA
GND
DSP_DATA
CD18_RESETn
IIS_SCLK
DSP_CLK
GND
CD18_SICL
AU_IIS_DATA
IIS_WCLK
CD_IIS_DATA
+5V
CD18_RAB
CD18_SILD
SPDIF_GND
SPDIF
DSP_FRAME
MP3-CD-2002 BOARD
(mask & flash version)
MP3-CD03 BOARD
(mask version)
2467
1u
1u
2462
2468
1u
2459
1u
3488
100K
3489
10K
*
3456
100R
10K
3499
7454-B
4
5
7
14
6
TRST
X1
96
X2|CLKIN
97
27
XF
INT3
25
IOSTRB
22
IS
32
MP|MC
26
MSC
24
MSTRB
NMI
63
PS
20
READY
19
RS
98
23
R|W
88
TCK
86
TDI
85
TDO
TMS
89
82
TOUT
87
135
HD7
6
HDS1
127
HDS2
129
HINT
51
30
HOLD
28
HOLDA
80
HPI16
HPIENA
92
HRD
Y
55
HR|W
18
IA
CK
61
29
IAQ
INT0
64
INT1
65
INT2
66
67
128
DVSS9
144
EMU0
83
84
EMU1|OFF
HAS
13
HBIL
62
HCNTL0
39
HCNTL1
46
HCS
17
HD0
58
69
HD1
81
HD2
HD3
95
120
HD4
HD5
124
HD6
D9
116
21
DS
DVDD1
4
33
DVDD2
D
VDD3
56
75
DVDD4
112
DV
D
D
5
DV
D
D
6
130
DVSS1
14
D
VSS2
40
D
VSS3
57
72
DVSS4
76
DVSS5
DVSS6
93
DVSS7
106
D
VSS8
111
CVSS9
99
D0
D1
100
D10
117
D11
118
D12
119
D13
121
D14
122
D15
123
D2
101
D3
102
D4
103
D5
104
113
D6
D7
114
D8
115
CVDD2
16
CVDD3
52
68
CVDD4
CVDD5
91
CVDD6
125
CVDD7
142
CVSS1
1
CVSS10
126
CVSS2
3
CVSS3
15
34
CVSS4
CVSS5
37
CVSS6
50
70
CVSS7
CVSS8
90
BDX0
59
74
BDX1
BDX2
60
BFSR0
43
36
BFSR1
44
BFSR2
BFSX0
53
73
BFSX1
BFSX2
54
31
BIO
77
CLKMD1
78
CLKMD2
79
CLKMD3
CLKOUT
94
CVDD1
12
A3
134
A4
136
A5
137
A6
138
A7
139
A8
140
A9
141
BCLKR0
41
BCLKR1
38
BCLKR2
42
BCLKX0
48
71
BCLKX1
BCLKX2
49
BDR0
45
35
BDR1
BDR2
47
A1
132
A10
5
A11
7
A12
8
A13
9
A14
10
A15
11
A16
105
A17
107
A18
108
109
A19
A2
133
110
A20
A21
143
A22
2
7451
A0
131
2466
100n
2458
*
1n
2463
3474
15R
1u
3465
100R
2451
1u
10K
3468
BC847BW
3
4
5
6
7
8
9
7456
1
10
11
12
13
14
15
16
17
18
19
2
6451
BZX384-C3V9
FMN
1451
pin allocation
MP3CD2002
to/from CD BO
ARD
MP3CD03
1k
3479
100R
3491
100R
3475
3476
100R
3471
3469
100R
33R
100R
3480
3481
100R
470R
3466
470R
3482
3498
3483
100R
1M
*
100k#
3492
3K3
2450
4450
100n
100R
3496
6450
BZX384-C3V3
for provision only
9
10
7
14
8
7454-C
3497
10K
4453
BC847BW
7460
VSS
7
WC_
M24C32
7458
1
E0
2
E1
3
E2
6
SCL
5
SDA
8
VCC
4
2452
1u
5
4
14
11
74HCT1G04
7457
2
3
NC
1
2453
100n
7454-D
4451
12
13
7
4452
10K
3485
180R
3458
3494
10K
1K
3456
10n
2458
2457
1K
3455
10n
2456
100n
3453
10R
15R
3451
1455
FMN
1
2
3
4
3452
100R
15R
3484
100n
2469
10K
3495
10K
3493
100n
2471
100n
2470
3491
100R
3467
10K
3449
100R
3450
15R
2454
2465
100n
100n
100n
2460
220u
2461
7455
1
4
IN
5
8
2
O1
3
O2
O3
6
O4
7
BC847BW
RESET
7453
10K
3464
1K
3460
7452
BC847BW
3459
220R
100R
#3462
#3463
100R
3473
100K
100K
3487
1460
CSTCE
5450
15R
3454
100n
2455
3457
680R
470R
3477
150K
3478
470R
3472
100n
2464
47R
3461
220u
2472
3
7454-A
74HC00D
1
2
7
14
3486
100R
3470
15R
42
DQ6
44
DQ7
30
DQ8
32
DQ9
9
NC
10
13
14
28
OE
RESET
12
15
RY|BY
VDD
37
27
46
11
WE
A8
8
7
A9
BYTE
47
26
CS
DQ0
29
DQ1
31
34
DQ10
36
DQ11
DQ12
39
DQ13
41
DQ14
43
DQ15|A-1
45
DQ2
33
DQ3
35
38
DQ4
40
DQ5
A10
6
5
A11
A12
4
3
A13
A14
2
1
A15
48
A16
17
A17
A18
16
23
A2
A3
22
21
A4
A5
20
19
A6
A7
18
Am29LV800B
7450
A0
25
A1
24
100R
3490
nRW
+3.3V
CD_IIS_DATA
DAT
A INTERF
ACE
CD10/CD18
+3.3V
uP_FRAME
SPDIF
from 1451
+3.3V
+3.3V
+5V
+3.3V
+3.3V
+3.3V
AD0
AD16
DD0
DD1
DD10
DD11
DD12
DD13
DD14
DD15
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
+1.5V
+core
SPDIF_GND
nMSTRB
IIS_SCLK
AU_IIS_DATA
+5V
uP_FRAME
SPDIF
to 1455
CD10_SILD
IIS_WCLK
CD10_SICL
+3.3V
uP_DATA
CONTROL INTERFACE
Front
µ
P
for 3.3V versions
only
+3.3V
uP_CLK
+1.5V
IIS_SCLK
A
U_IIS_D
A
T
A
CD10_SICL
CD10_SD
A
CD10_RAB
CD10_SILD
S
TAT
U
S
from 3461
uP_CLK
uP_D
A
T
A
nCD10_RESET
AD3
AD4
AD5
AD6
AD7
AD8
AD9
DD0
DD1
DD10
DD11
DD12
DD13
DD14
DD15
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
+3.3V
SPDIF_GND
nCD10_RESET
CD10_RAB
CD10_SDA
nPS
TMS_RESET
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD17
AD18
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD0
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD2
+core
+core
+core
CD_IIS_DATA
IIS_WCLK
+core
+core
nPS
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
nRW
nMSTRB
MP3CD2002 mask+flash/MP3CD03 mask only, 060204
100R
3461
to
7451/124
for MP3CD03
for MP3CD2002
STATUS
FOR ORIENTATION ONLY
CONTR
OL INTERF
A
C
E
CD10/CD18
MP3 B
OARD
- C
IRCUIT
D
IAGRAM