EN 36
3139 785 31500
7.
Circuit Diagrams and PWB Layouts
Analog: Digital In / Out 1 (DIGIO 1)
1
1
1
1
1
1
I708 D5
I709 D7
I710 D8
I711 D8
7700-6 B3
F700 C8
F701 C8
F702 C8
F703 C8
I702 D1
I707 E5
from DAC_ADC
OUT
S
P
m
orf
3712 D7
3713 E7
5700 D6
7700-1 D3
7700-2 E4
7700-3 D4
7700-4 F4
d
e
s
u t
o
n
ID0
DIGITAL
7700-5 E4
3701 A4
3702 B4
3703 B3
3704 B4
3705 C2
3706 D1
3707 E1
3708 D2
3709 E3
3710 E5
C
D
E
F
A
B
C
to DAC_ADC
*
*
2702 D2
2703 E5
2704 D5
2705 D8
2706 D7
3700 A3
7
8
9
1
2
3
4
*
*
5
6
7
8
9
A
B
1
2
3
4
5
6
E
F
0006 F2
1700 C9
1701 D9
2700 A4
2701 A4
Digital In/Out 1 DIGIO1
OPTION
d
e
s
u t
o
n
*
I712 A4
i713 B3
I714 D4
I715 D2
I716 E3
I717 D3
to DAC_ADC
2
OI
GI
D
ot
D
3712
75R
R
0
6
5
5
0
7
3
2
0
7
3
K
0
0
1
82R
5V1
3713
5V
5V
I714
5V1
74HCU04D
13
7
14
12
1700
310360100162
1
2
3
4
7700-6
R
0
6
5
0
1
7
3
100n
2704
R
0
7
4
0
0
7
3
I702
F701
F700
YKC21-3416
1701
1
3
2
F703
3
7
14
4
5V1
8
7700-2
74HCU04D
74HCU04D
7700-4
9
7
14
2K2
3709
2702
100n
n
0
1
0
0
7
2
7700-3
74HCU04D
5
7
14
6
7700-5
11
7
14
10
I716
74HCU04D
100R
3703
7
0
7
3
R
0
0
1
750R
I710
3706
V
0
1
1
0
7
2
0
u
1
K
0
0
1
1
0
7
3
I709
0006
BRACKET
5
0
7
2
p
0
5
1
10K
3704
i713
5V1
F702
I715
I711
I717
7700-1
1
7
14
2
74HCU04D
470R
3708
2706
I708
5V
100n
I712
5V1
5V1
V
5
I707
3
2
6
4
049S20056
5700
0
n
1
3
0
7
2
DAINOPT
DAINCOAX
DAOUT
3139_243_32694_a3_sh130_sh7.pdf 2005-07-08