EN 57
3139 785 30981
8.
Circuit- and IC description
Video
Part
The analogue video input signals CVBS (Rear, Front,
Tuner) and YC (Front) are routed via the board to
connector 1521 and sent to the Video Input Processor,
TVP5146P [7401]. The digital video input signals from
the DV-in on the Front board are routed from connector
1521 via the IEEE 1394 PHY IC [7301] to the Domino chip
[7101].
The Video Input Processor encodes the analogue video
to digital video stream (CCIR656 format). The output
stream, named VID_D (9:0), is then routed to the Domino
chip. This IC encodes and decodes the digital video
stream into / from MPEG2 format.
Audio
Part
I
2
S audio is sent from the Analog board to the Domino
chip via connector 1536.
The Domino chip compresses the I
2
S audio data into an
MPEG1-L2 / AC3 audio stream.
Front-end I
2
S
The Domino chip interfaces directly to the basic Engine
via ATAPI connector 1571.
It buffers the data streams that are coming from (or going
to) the Basic Engine.
In the Domino chip, the video MPEG2 stream and the
audio AC3 stream are sent to the basic Engine for
recording through ATAPI bus.
8.4.2. Playback
mode
During playback, the data from the Basic Engine is going
directly to the Domino chip via ATAPI interface. The
Domino chip has the following outputs:
•
Analogue video CVBS, YC and RGB outputs on
connector
1521
•
I
2
S audio (PCM format) on connector 1536
•
SPDIF audio (digital audio output) on connector 1536
•
Progressive Scan output connector 1522 (Not for
European
version)
8.4.3. Basic Engine Interface
The Digital board is equipped with an IDE bus (ATAPI) for
connecting to the Basic Engine.
FRONTEND INTERFACE
VIP
TVP5146
DMN 8652
7101
7401
7301
1934 PHY
24.576 MHz
14.31818MHz
13.5 MHz
7211
SDRAM
7231
SDRAM
150 MHz
HARD DISK
INTERFACE
Figure 8-5 DIMINO_CLOCK
The Domino chip has a complex system, which is needed
to support the processes running at different frequencies
such as video decoding, audio decoding or peripheral
I/O devices etc. To ensure a synchronous initialization
of all the registers and state machines, all the PLLs are
switched to their default frequency 27MHz.
Then when the booting control unit is correctly initialized
and once it has captured all the booting parameters, it
sets the PLLs to its functional frequencies. Thanks to a
clock blocking mechanism, the frequency switching is
glitch free.
System clocks:
•
DMN-8652 (7101, pin A1 and A2) : 13.5 MHz provided
by the x’tal 1101
•
DMN-8652 1394-LINK (7101, pin K1) : 49.152MHz
provided by 1394-PHY
•
TVP5146 (7401, pin 74 and 75) : 14.31818MHz
provided by x’tal 1461
•
SDRAM (7211 and 7231, pin 45 and 46) : 150MHz
provided by the DMN-8652
•
TSB41AB1PHP IEEE 1394 PHY IC (7301, pin 42 and
43) : 24.576MHz provided by x’tal 1351
8.4.4. Clock
Distribution
