Video Signal Flow block (Figure 15)
The Tuning system will tune all of the channels in the ATSC, NTSC, and Cable bands. Whichever
channel is selected by the Customer, the video signal is converted to a Digital 8-bit TMDS signal.
This signal is fed to the Scaler IC on the HD/DW panel. Composite or SVHS NTSC signals are fed
to the set via the Side Jack panel, AV1, or AV2. These signals are fed to a Switch located on the
SSM (Small Signal Module). The selected Composite or YC signal is then fed to the HIP circuit on
the SSB where it is changed to a YUV signal. The YUV signal is fed to the HD/DW module for digi-
tal processing. The AV3 and AV4 Component signals are fed directly to the HD/DW module. Digital
480p, 720p, or 1080i is fed to the HD/DW module via the HDMI input. The Scaler on the HD/DW
module resizes the picture to 1080i. The 1080i signal is then output to the SSM to the HOP and
CRT drive circuits. OSD (On-Screen Display) generated by the Processor on the SSB is fed to the
HOP to be inserted into the CRT RGB signals. Horizontal and Vertical from the HOP is fed to the
LSB (Large Signal Board) to drive the Scan circuits.
Side Jack Panel (Figure 16)
The Side Jack panel has a Composite Video and SVHS input. When there is a connector in the SVHS
input, the Composite input is muted. Resistors 3001, 3002, and 3000 on the Video, Y, and C lines pro-
vide 75-ohm impedance matching. If a cable is plugged into the SVHS connector, the line connecting
resistor 3029 to ground is removed causing the voltage on the Y/C_CVBS_SENSE_FRNT line to
increase. This signals the Microprocessor to switch the video switching circuits from composite video to
YC in.
NTSC AV inputs and switching (Figure 17)
AV1 and AV2 Composite and SVHS inputs are located on the SSM. These inputs as well as the
Side Jack panel are fed to the Video Switch, 7017. This IC is controlled by the Processor on the
SSB via the SCL_IN and SDA_IN bus. Composite video or Luminance is output on Pin 1 and
buffered by 7003 before being fed to the SSB. The Chroma signal is output on Pin 3 and buffered
by 7102. If a SVHS signal is connected to one of the AV inputs, the S-1, S-2, or S-3 lines will go
Low for that respective input. The Processor will read these Pins via the I2C bus and signal the HIP
that the signal present is YC instead of Composite.
Page 21
Summary of Contents for DPTV400 Series
Page 9: ...7 FIGURE 3 EPIC REAR JACK PANEL Page 6 ...
Page 14: ...FIGURE 6 STANDBY POWER SUPPLY Page 11 ...
Page 15: ...FIGURE 7 MAIN POWER SUPPLY Page 12 ...
Page 20: ...FIGURE 11 HORIZONTAL OUTPUT Page 17 ...
Page 21: ...FIGURE 12 HIGH VOLTAGE Page 18 ...
Page 22: ...FIGURE 13 VERTICAL AMPLIFIER Page 19 ...
Page 25: ...FIGURE 15 VIDEO SIGNAL FLOW BLOCK Page 22 ...
Page 26: ...FIGURE 16 SIDE JACK PANEL Page 23 ...
Page 27: ...FIGURE 17 SSM NTSC AV INPUTS AND SWITCHING Page 24 ...
Page 29: ...FIGURE 18 NTSC SSB SIGNAL PROCESSING Page 26 ...
Page 30: ...FIGURE 19 HD ATSC BLOCK Page 27 ...
Page 31: ...FIGURE 20 EPIC ATSC BLOCK Page 28 ...
Page 32: ...FIGURE 21 HD DW MODULE Page 29 ...
Page 35: ...FIGURE 23 AV3 AND AV4 INPUTS AND SWITCHING Page 32 ...
Page 38: ...FIGURE 25 SSM VIDEO DRIVE Page 35 ...
Page 41: ...FIGURE 26 SHARPNESS CONTROL Page 38 ...
Page 42: ...FIGURE 27 TINT CONTROL Page 39 ...
Page 43: ...FIGURE 28 CRT DRIVE Page 40 ...
Page 45: ...FIGURE 30 CRT PANEL Page 42 ...
Page 47: ...FIGURE 31 AUDIO SIGNAL FLOW BLOCK Page 44 ...
Page 48: ...FIGURE 32 SSB AUDIO PROCESSING Page 45 ...
Page 49: ...FIGURE 33 AUDIO AMPLIFIER Page 46 ...
Page 52: ...FIGURE 35 CONVERGENCE PROCESSOR Page 49 ...
Page 53: ...FIGURE 37 INTELLISENSE SENSING CIRCUIT Page 50 ...
Page 55: ...FIGURE 38 CONVERGENCE HORIZONTAL DRIVE Page 52 ...
Page 56: ...FIGURE 39 VERTICAL CONVERGENCE DRIVE Page 53 ...
Page 58: ...FIGURE 40 SET CONTROL AND I2C BUSSES Page 55 ...
Page 59: ...FIGURE 41 OSD SIGNAL PATH Page 56 ...
Page 62: ...Figure 59 FIGURE 42 WIRING INTERCONNECT ...
Page 71: ...FIGURE 44 SAM MENUS Page 68 ...
Page 77: ......
Page 78: ...MMARTIN 04 13 04 ...