Circuit Descriptions
7.
7.6
I
2
C
Refer to
for the I
2
C architecture.
Figure 7-8 I
2
C architecture
7.7
TCON
The Timing Controller is integrated in the SSB (“Forward
Integration” concept). Refer to
for the TCON system
block diagram.
Figure 7-9 TCON system block diagram
1
8
970_207_100
3
25.ep
s
100
3
25
MT5
3
92
NVM
7605
10k
+
3
V
3
_
S
W
10k
22R
22R
O
S
DA0 (J
3
0)
O
S
CL0 (J29)
S
DA-MAIN
S
CL-MAIN
Am
b
ilight
μ
Controller
7
8
01
100R
100R
4k
7
+
3
V
3
_
S
W
4k
7
47
4
8
AMBI_
S
DA
AMBI_
S
CL
O
S
DA1 (K
3
0)
O
S
CL1 (K29)
HDMIMUX
7900
22R
DDC_
S
CL
DDC_
S
DA
O
S
DA2 (AJ10)
O
S
CL2 (AK10)
67
6
8
40
27
100R
ForDe
bu
gging
100R
10K
10K
+
3
V
3
_
S
W
4k
7
+
3
V
3
_
S
W
4k
7
1R
1R
TUNER_
S
DA
TUNER_
S
CL
100R
FRONTEND_
S
DA
FRONTEND_
S
CL
100R
15p
15p
TUNER
1205
12
1
3
L2
8
L29
47p
5
6
10p
10p
1
8
920_209_100
3
1
8
.ep
s
100
3
19
EEPROM
TFT – LCD P
a
nel
Mini - LVD
S
Control
S
ign
a
l
s
+
3
V
3
+ 1V2
VGH (+
3
5V)
VGL (
−
6V)
+12V
LVD
S
(10
b
it)
Timing
Controller
Power
Block
G
a
mm
a
Reference
Volt
a
ge
S
o
u
rce Drive IC
G
a
te Drive
IC
MTK
LCD P
a
nel
TCON
M
a
in Pl
a
tform
SS
B
+ 15.6V