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Circuit Descriptions
7.
Figure 7-2 Architecture LC9.3L LA chassis - detailed
1
8
970_202_100
3
25.ep
s
100
3
25
CVI1/2+A
u
dio L/R
AV IN A
u
dio L/R
OFDM
demod
CVB
S
2 × CVI
Q
ua
d LVD
S
1920 × 1080p@ 100Hz
HDMI v1.
3
U
S
B2.0
- JPEG
- MP
3
- MPEG4
S
PDIF o
u
t
2pc
s
3
2 M ×
3
2 (1G
b
it)
GDDR
3
DC-DC
12V
3
V
3
s
t
b
y
S
eri
a
l T
S
S
PDIF
5V
3
V
3
1V05
1V
8
1V2
S
h
a
rp
4:1 M
u
x
(ADV
3
002
)
8
V
au
dio
DVI A
u
dio
5V
I/O:PWM/B
a
cklight
Tcon/P
S
U/.. control
s
u
P
M
u
x
ADC
Video/A
u
dio
proce
ss
or
Pixel
proce
ss
ing
/
S
c
a
ler
MT5
3
92
1.
8
V
5V
3
V
3
3
.
3
V
Am
b
ilight
1 G
b
it NAND
VGA
EDID
EDID
Power
a
mplifier