Philips A02E Service Manual Download Page 72

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Circuit Descriptions, Abbreviation List, and IC Data Sheets

Figure 9-18 ADOC control block diagram

9.7.2

Internal Bus Structure

PI Bus
The Peripheral Interconnect (PI) bus connects all of the
functional blocks within the ADOC device. Physically it is split
into four distinct sections. These are referred to as:

•

Fast PI Bus.

•

Slow PI Bus.

•

Video PI Bus.

•

Sound PI Bus.

The individual segments of the PI bus are interconnected via
PI-PI bridges. When several devices are connected to a bus
system section only one of these may have control (ownership)
of the bus section at any instant in time. The device that has
control is referred to as the bus master, the remaining devices
are referred to as slaves. Each bus segment section has a Bus
Control Unit (BCU), which allocates bus ownership to the
various modules that are capable of being bus masters. A bus
master may have ownership of one or more sections of the PI
bus.

Extension Bus Interface Unit
The Extension Bus Interface Unit (EBIU) allows various types
of memory (ROM/FLASH/SRAM) to be attached to the ADOC
IC and must therefore be configured per memory type (in terms
of chip select lines, bus width used, and access times). This
enables the hardware of the EBIU to correctly address the
external memories and apply the correct number of wait states.

9.7.3

Microprocessor Reset

The reset of the device is split between three functions:

•

Power-On-Reset (POR). Output is fed to the Power Clock
Reset (PCR) block generating a Hard reset (all functions
reset).

•

PCR. In simplified terms two outputs are available:

–

Hard reset, all blocks within ADOC are reset.

–

Soft reset, a limited number of blocks within the control
core are reset.

•

GP registers are used to allow software control of the reset
to certain blocks within ADOC.

9.7.4

External Bus Structure

I2C Bus
The system has two system I2C buses; one for the devices on
the SSB and the other for the devices used in the external
modules .

•

The I2C-1 system bus, comprises of SCL and SDA, is used
to control all the I2C devices on the LSP (the main tuner)
and other I2C devices connected to other external panels
(PIP Front-End demodulation IC, PIP tuner, etc.). The I2C-
1 is a 100 kHz bus and is called as "slow" bus. It is
connected to the +5V supply. All these devices are
powered down in the Standby mode.

•

The I2C-2 system bus, comprises of SCL2 and SDA2, is
used to control all the I2C devices (MPIF, 3D-Comb, NVM,
etc.) present on the SSB. The I2C-2 is a 400 kHz bus and
is called as "fast" bus. It is connected to the +3.3V supply.

9.8

Protections

For a detailed description, see chapter 5 "Service Modes, Error
Codes, and Fault Finding".

9.9

Software Upgrading

In this chassis, you can upgrade the software via ComPair.
This offers the possibility, to replace the entire SW image
without having to remove the flash-RAM from its socket. You
can find more information on how this procedure works in the
ComPair file. It is possible that not all sets are equipped with
the hardware, needed to make software upgrading possible. To
speed up the programming process, the firmware of the
ComPair interface can be upgraded. See Chapter "Service
Modes ..."; paragraph "ComPair" - “How To Order” for the order
number.

CL 36532058_075.eps

071003

MIPS

EBIU

SRAM

128KB

PI-PI

BRIDGE

GFX

GEN

GPIO

I2C