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Circuit Descriptions, Abbreviation List, and IC Data Sheets

Figure 9-8 MPIF Audio source selection

A to D Converters
The MPIF contains four video ADCs for analogue and digital
video broadcast signals. The clock frequency for these ADCs
is either 27 MHz or 54 MHz. In some cases, two analogue
signals are multiplexed at the input of one ADC. In these cases,
the clock frequency of the ADCs is 54 MHz, while the sample
frequency for each of the two signals is 27 MHz.

The sample frequency for standard 1fH video signals is 27
MHz.
For the YUV channel the sample frequency of the U and V
components is half the sample frequency of the Y signal.
For 2fH YPbPr or RGB input signals (for instance 480p or 1080i
ATSC signals), the frequency that is used to sample the YUV
signals is twice as high as for 1fH signals. The sample
frequency is 54 MHz for Y and 27 MHz for U and V.
Due to the high sample frequency, two data links are needed
for transport of the video data to the digital video processor.

9.4.2

Data Link Interface (I2D)

The digital interface between MPIF and ADOC is called Data
Link (or I2D Link). Data Link is a pin efficient, EMC friendly and
power efficient serial interface that transfers the data from
MPIF to ADOC over three Data Link interfaces. Each Data Link
has a data signal and a strobe signal. The synchronisation
information is distributed over the data and the strobe signal.
To minimize EMC, both signal outputs are low voltage
differential swing signals, with a swing of about 300 mV.
Each Data Link has four lines, one differential pair for the data,
and one differential pair for the strobe. The data rate is 594
Mbit/s. Each Data Link can carry two 27 MHz sampled video

streams (or one 54 MHz sampled 2fH video stream) and two
audio channels sampled at 6.75 MHz.

In the MPIF, the (video and audio) data to be transmitted is
multiplexed in an output register of 42 bits. The content of that
42 bits register is serial transmitted on one of the three data
links. In the ADOC, the serial data is de-multiplexed into
parallel streams. The data on the data link is divided in several
groups of signals (video, audio and strobe signals). Obvious it
is important that the transmitter and receiver are in the same
transmitting mode.

9.4.3

ADOC Digital TV Processor

Introduction
The A02 system is built around the ADOC IC. This chip
implements all TV functions in digital technology. Only a few
functions (like AD-conversion, IF processing and source select)
are implemented in an analogue companion IC, the MPIF.
The ADOC (Analogue Digital One Chip, type number
PNX3001-3008, item number 7300) is a fully integrated,
digitally implemented TV processor for audio, video, VBI
services, graphics, and control. It is a global, multi-standard
system primarily designed for the reception and processing of
analogue broadcast signals.
An integrated MIPS 1910 processor runs the chassis software.
This software is stored in a non-volatile external flash memory
(item 7790). Following figure shows the ADOC block diagram.

CL 36532058_074.eps

071003

prim

A/D

Mono

sec
A/D

Line

Scart

AUDIO

AMPs

LPF

L prim