10-5
Digital Main 2 Schematic Diagram
OPEN
C3009
0.1
C3012A
OPEN
C3003
0.1
C3002
OPEN
C3005
L3001
OPEN
4.7K
R3007
OPEN
C3010
10K
R3002
D3002
OPEN
D3003
OPEN
D3004
OPEN
0R3006
0.1
C3004
100
R3005
51
R3001
4.7K
R3008
100
R3004
51
R3003
OPEN
C3001Z
OPEN
C3006
1C3007B
OPEN
C3011
TUNER+3.3V
100
R9001
3 SDA
CN3002
1 IF-AGC
4 GND
2 SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 17
19
20
21
22
23
24
DSP
/FILTER
PGA ADC
RF
AGC
OUTPUT
I/F
IC9001
SI2151
NU
SDA
SCL
NU
IF-AGC
GND
VDDL
GND
VCC
NU
XTAL-I
XTAL-O
VCC
GND
VCC
NU
RF-REF
RF-IP
GND
GND
NU
OPEN
C9019
1000P
C9008 1C9009
1P
C9023
1000P
C9010
100
R9005
100
R9004
1P
C9021
1P
C9022
X9001
24MHz
1
3
4
2
100P
C9018
C9014
VARISTOR
220P
C9004
L9001
270nH
100P
C9002
L9002
220nH
220P
C9003
3P
C9015
L9007
5.6nH
1P
C9017
L9004
270nH
L9003
270nH
1000P
C9006
220P
C9005
L9006
270nH
L9005
270nH
100
R9003 0.1
C9007
OPEN
C9011 OPEN
C9012 OPEN
C9013
OPEN
C9016
OPEN
C9020
100
R9002
JK9301
560P
C9001
AK4
IC3001(2/8)
*1
MSD95NTGW8D-3-0BJG
AF7 TU-SDA
AE7 TU-SCL
AJ2 IF-AGC
AJ4
OPEN
C9025
AE4 HP-DET
AH3 NU
AJ3 GND
AK2 GND
AK3 GND
AH4 GND
L3003
2.2uH
L3002
BEAD
0.1
C3104
33
R3113
0.1
C3103
33
R3114
22
R9006
D3001
OPEN
33P
/100V
C3927
33P
/100V
C3926
HP-DET
P-ON+3.3V
10
C9024
OPEN
C3012B
100
R3030
OPEN
C3007A
10
C3013
10
C3008 OPEN
C3008Z
OPEN
C9015Z
0.033
C3001
OPEN
C3001ZZ
DIGITAL SIGNAL PROCESS
/MAIN MICRO CONTROLLER
DEMODULATOR
/MPEG
DECODER
TO DIGITAL
MAIN 5
IC3001(5/8)
TO DIGITAL
MAIN 5
IC3001(5/8)
2
4
3
1
G
K
I
H
J
L
DIGITAL MAIN CBA UNIT
CONTINUE
DIGITAL 8
(NO CONNECTION)
DIGITAL/ANALOG
TV TUNER
ANT-IN
CONTINUE
DIGITAL 5
The order of pins shown in this diagram is different from that of actual IC3001.
IC3001 is divided into eight and shown as IC3001 (1/8) ~ IC3001 (8/8) in this Digital Main Schematic Diagram Section.
1 NOTE:
PL22.06SCD2