9-3
3. Digital Signal Process Block Diagram
DIGIT
AL MAIN CB
A UNIT
IC3001
(DIGIT
AL SIGNAL PR
OCESS)
DIGIT
AL
SIGNAL
PR
OCESS
HDMI-IN3
HDMI-IN2
JK3701
D
A
T
A0(+)
ARC
ARC-OUT
D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK
7
14
9
4
6
1
3
10
12
16
15
7
9
4
6
1
3
10
12
16
15
JK3703
CLOCK(+)
CLOCK(-)
A
UDIO
DECODER
HDMI
I/F
HDMI SW
T
O
VIDEO/A
UDIO
BLOCK DIA
GRAM
VIDEO
DECODER
VIDEO SIGNAL
AUDIO SIGNAL
D
A
T
A(0-7)
IC3102
(NAND FLASH MEMOR
Y)
EMMC-D
A
T(0-7)
A/D
CONVER
TER
SW
CVBS-VIDEO-IN
DEMODULA
T
O
R
/MPEG DECODER
A
UDIO I/F
DIF-OUT2
DIF-OUT1
IF-A
GC
IF-A
GC
LVDS
TX
DDR3-DQ(0-15)
DDR3-DQ(16-31)
DDR3-A(0-15)
D
ATA
ADDESS
IC3402
(DDR3 SDRAM)
D
ATA
ADDESS
IC3401
(DDR3 SDRAM)
A
UDIO(L)-OUT
A
UDIO(R)-OUT
SPDIF
CVBS-
A
UDIO(L)-IN
CVBS-
A
UDIO(R)-IN
HP(L)
HP(R)
D
A
T
A0(+)
D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK
CLOCK(+)
CLOCK(-)
AC
6
AF4
AF5
AF2
AF1
AG
5
AG
4
K6
AA4
J3
H2
K3
J2
K1
K2
H3
G2
P6
P5
T3
R2
U3
T2
V3
U2
R1
R3
U6
W6
AK4
AJ4
AJ2
HDMI-IN1
7
9
4
6
1
3
10
12
16
15
JK3702
D
A
T
A0(+)
D
A
T
A0(-)
D
A
T
A1(+)
D
A
T
A1(-)
D
A
T
A2(+)
D
A
T
A2(-)
HDMI-D
A
T
A
HDMI-CLOCK
CLOCK(+)
CLOCK(-)
W2
W1
V2
Y3
AA2
AA3
W3
V1
Y6
AA5
AA30
AB29
AA28
A
G30
AD29
A
C28
A
C29
AA29
AE29
AE30
AE28
A
G28
A
G29
AJ25
AH25
AH30
AH29
AF29
CN3901
LCD P
ANEL
ASSEMBL
Y
24
23
21
20
18
17
15
14
12
11
9
8
6
5
3
2
26
27
RX0(+)
RX0(-)
RX1(+)
RX1(-)
RX2(-)
RX2(+)
RX3(-)
RX3(+)
RX4(-)
RX4(+)
RX5(-)
RX5(+)
RX6(-)
RX6(+)
RX7(-)
LOCKN
RX7(+)
HTPDN
PL22.06BLD