Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 132
BP2.2U, BP2.3U
9.
9.17.4 Diagram B3x, PNX3000HL (IC 7C00)
Figure 9-33 Internal block diagram and pin configuration
Block Diagram
MCE430
2
10
10
10
4
2
2
2
2
CVBS
PRIM.
SWITCH
CVBS/Y_PRIM
CVBS_SEC
CVBS0
VIFIN
SIFIN
DTVIFIN
DTVIFAGC
TUNERAGC
DTVIFPLL
VIFPLL
CVBS_IF
CVBS1
CVBS2
CVBS/Y3
C3
CVBS/Y4
C4
YCOMB
CCOMB
CVBS_DTV
VIF
PLL
&
DTVIF
MIXER
2
2
QSS
MIXER
&
AM SND
DEMOD
Fpc
CVBSOUTIF
2nd SIF internal
DTV 1st IF
DTV 2nd IF
CVBSOUTA
CVBSOUTB
2NDSIFEXT
(FMRAD)
SIFAGC
VIF
AMP
2
SIF
AMP
IF
SWITCH
SNDTRAP
&
GROUP
DELAY
VIDEO
IDENT
2ndSIF
AGC
DET
2NDSIFAGC
SWITCH
PNX3000
1
×
A
D
VCA
CVBS
OUT
SWITCH
&
CVBS
SEC.
SWITCH
CLP_SEC
CLK
CLK
Yyuv
U
V
L
R
L
297 MHz
297 MHz
ICLP
CLP_PRIM
AUDIO SWITCH
(ANALOG OUT)
AUDIO SWITCH
(DIGITAL OUT)
AUDIO
AMPS
AM
EXT
L1
L2
L3
L4
L5
DSNDR1
DSNDL2
DSNDR2
R1
R2
R3
R4
R5
DSNDL1
LINEL
LINER
SCART1L
SCART2R
EWVIN
EWIOUT
REW
ADR SCL SDA
IRQ
HV_PRIM
VAUD
VAUDO
VAUDS
XREF
13.5 or 27 MHz
HV_SEC
CLP_PRIM
CLP_SEC
CLP_YUV
SCART1R
SCART2L
VOLTAGE
TO
CURRENT
I
2
C-BUS
INTERFACE
TIMING
CIRCUIT
DIVIDER
VD2V5
RREF
27 MHz
54 MHz
13.5 MHz
ADC
CLOCK
PLL
DATALINK
PLL
BAND
GAP
REF
DATA
LINK 2
DATA
LINK 3
MIC
AMPS
MIC2
MIC2
MIC1
MIC1
R1/PR1/V1
CLP_YUV
AM sound
ICLP
G1/Y1/Y1
B1/PB1/U1
R2/PR2/V2
G2/Y2/Y2
B2/PB2/U2
AM
int
RGB/YUV
MATRIX
&
SWITCH
VDEFL
VDEFLS
VDEFLO
BGDEC
DLINK3
4
DLINK2
C
10
4
A
D
CLK
ICLP
ICLP
297 MHz
DATA
LINK 1
DLINK1
2
DTVOUT
A
D
CLK
297 MHz
A
D
A
D
6.75 MHz
R2/MIC2/AM
R
A
D
L2/MIC1/PipMono
A
D
R1/AMext
primary digital audio
secondary digital audio
A
D
L1/AMint
Pin Configuration
F_15400_131.eps
240505