7.
Circuit Diagrams and PWB Layouts
SSB: Dolby Digital Decoder
B6a,d
B6a(2x),C
AND
DOLBY DIGITAL
DOLBY DIGITAL DECODER
B
C
D
E
F
2AC1 B4
MPEG-1 LAYER-2
B6c
1
2
3
4
5
6
7
8
9
1
2
3
4
5
B6a
B14b
B6a(2x),C
AUDIO DECODER
B6c
2AD3 B4
2AD4 B6
2AD5 B5
2AD6 B6
2AE2 D8
6
7
8
B6a,d
3V1
B6a,C
7A30 B4
IA71 D7
IA72 D7
IA75 D7
9
A
B
C
D
E
F
A
B6c
B14b
2AD0 B6
2AD1 B6
2AE3 D7
2AE5 D7
2AF0 E6
2AF3 C8
2AF4 C7
3A74 D7
3A77 E7
5A38 B8
B6c
4V9
100n
2AF4
220p
2AC1
3A74
75R
2AD0
1n0
2AD5
1n0
+5M
75R
3A77
2AD4
1u0
1u0
2AD3
2AF0
10n
+5M
1n0
2AD6
23
XVDD
22
XVSS
43
_EOD
36
_PCS
5
_POR
42
_RTR
41
_RTW
40
SPDI_2
39
SPREF
44
SYNC
6
TE
2
VDD
1
VSS
9
XTI
10
XTO
25
SOC
27
SOD
14
SOD1
15
SOD2
16
SOD3
26
SOI
17
SPDIFOUT
38
SPDI_1
4
SCL
3
SDA
19
SIC
32
SIC_PI16
21
SID
30
SID_PI14
20
SII
31
SII_PI15
28
PI12
29
PI13
33
PI17
34
PI18
35
PI19
18
PI4
24
PI8
37
PR
8
AVDD
7
AVSS
13
CLKO
11
NC1
12
NC2
7A30
IC MAS3528E
IA75
A8
+5M
5A38
2AD1
1u0
A2
+5M
100u
2AF3
10n
2AE5
1n0
2AE2
IA71
IA72
+5V
+5M
2AE3
10n
A4
SCL-F-AUD
SDA-F-AUD
I2S-MSP-CLK
I2S-MSP-OUT
I2S-MSP-WS
SYS-CLK1
SYS-RESET
A5
SPDIF-IN1
SPDIF-BO-OUT
I2S-DD-OUT
I2S-DD-CLK
I2S-DD-WS
A3
A6
A7
B6B
B6B
F_15460_024.eps
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8204 000 8477.1