IC Data Sheets
8.
8.4
Diagram
B11, MT5136AN (IC U103)
Figure 8-6 Internal block diagram and pin configuration
19430_306_130129.eps
130129
Block diagram
Pinning information
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
TS_DATA1
GPIO1
DVDD33
GPIO1
DVDD11
TS_DATA0
TS_SYNC
TS_VAL
TS_CLK
SDA
SCL
DGND33
DVDD33
TUNER_CLK
TUNER_DATA
CHIP_CTRL
DVDD11
AVDD33_IFPGA
AVDD12_DEMOD
IFPGA_INP
IFPGA_INN
AVSS12_DEMOD
EXT_CLKSEL
AVDD33_XTAL
1
2
3
4
5
6
7
8
9
10
11
12
3
6
3
5
3
4
33
3
2
3
1
3
0
29
2
8
27
26
25
DVDD
33
R
S
TN
DVDD11
AVDD
33
_R
SS
I
ADINO
LOUTN
LOUTP
AVDD
33
_DEMOD
AV
SS33
_DEMOD
XTALI
AV
SS33
_XTAL
XTALO
T
S
_DATA2
T
S
_DATA
3
T
S
_DATA4
DVDD11
DVDD
33
T
S
_DATA5
T
S
_DATA6
T
S
_DATA7
T
S
_ERR
DVDD11
RF_AGC
IF_AGC
MT5136AN
RF
Tuner
RSSI
RF AGC
Differential
IF signal
Tuner SDA
Tuner SCL
RSSI ADC
AGC
PGA
10-bit
ADC
Integrated SAW
filter function
DVB-C
demodulator
TSIFMUX
SIF Master
Micro-
controller
DVB-T
demodulator
DVB-T
demodulator
Demod TS
MT5136AN
DVB-T/C FEC
decoder
SIF
transceiver
SIF interface
Main
decoder
chip
DVB-T/C FEC
decoder