PerkinElmer
Optoelectronics
8
4.2.1 MCLK Input
The master clock signal (MCLK) is an optional clock input applied when the user
desires a clock rate different from the default rate for the camera. The MCLK
signal is limited to be between 2 MHz and the maximum clock rate allowed for
the selected camera and may be applied in all camera operating modes. When
MCLK is applied, the camera output signals CCLK and LEN are synchronized to
MCLK to assure a locked video output.
Note:
The MCLK input is automatically detected on the camera. If no MCLK input is
present or if MCLK becomes disconnected, the camera will default to its default
clock rate.
4.2.2 Digital Output
The digital video is output together with two synchronization signals: Camera
Clock (CCLK), and Line Enable (LEN). The LEN signal brackets the valid
digital video that is output in synchronization with the CCLK.
Note 1.
Since the camera electronics stores a video line in memory prior to sending it to
the output, when operating in the slave mode, the first line output after the first
LT has been issued is not valid.
Note 2.
CCLK – Digital video data can be sampled using the rising edge of the CCLK
signal..
4.2.3 Master Mode
The master mode is a stand-alone operating mode that requires only DC power
for operation.
Figure 5 Master Mode Timing (LVDS Model)
The exposure time in master mode is determined by the line period that is fixed at
N+76 clock cycles, where N is the number of pixels. See Table 2 for a listing of
Summary of Contents for RETICON LD3500 Series
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