Introduction
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7
1.4. BLOCK DIAGRAM
×
Figure 1.1
Ø
CACHE
CPU
ICW
42C25
Data
Address
Control
60/66 MHz
30/33 MHz
14.318 MHz CLOCK Generator
MA
RAS
CAS
WE
M1451
DRAM
PCI
IDE
IDE1
IDE2
PCI BUS
ISA
SLOT1-4
M1449
UMC
I/O
Floppy
LPT
COM1
COM2
ISA BUS
PCI
SLOT1-3
AD
Control
1.5. INTRODUCE THE PCI - BUS
Connecting devices to a CPU local bus can dramatically increase the speed of
I/O-bound peripherals with only a slight increase in cost over traditional systems.
This price / performance point has created a vast market potential for local bus
products. The main barrier to this market has been the lack of an accepted
standard for local bus peripherals. Many mainboard and chipset manufactures
developed their own local bus implementations, but they are incompatible with
each other. The VL (Video Electronics Standards Association) local bus and PCI
(Peripheral Component Interconnect) bus specification was created to end this
confusion.
The PCI - bus standard, under development since Jun. 1992, which is designed
to bring workstation-level performance to standard PC platform. The PCI - bus
removes many of the bottlenecks that have hampered PC for several years. On
the PCI - bus, peripherals operate at the native speed of the computer system,
