BIOS Configuration
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4.7. CHIPSET FEATURES SETUP
ROM PCI / ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: Select Item
L2 Cache Update Policy
: Write Back
ESC
F1
F5
F6
F7 : Load Setup Defaults
: Quit
: Help
: Old Values
: Load BIOS Defaults
PU/PD/+/-
(Shift)F2
: Modify
: Color
Cache Wait / 1 = 66, 0 = 60 MHz : 0 Wait
DRAM Timing Option
DRAM Refresh Peroid
Hidden Refresh Control
15 - 16 M Memory Location
: Normal
: Long
: Local
Onboard PCI / IDE chip
: Enable
: Enabled
: Enabled
Onboard FDD Controller
Onboard Parallel Mode
Onboard Parallel Port
Onboard Serial Port1
Onboard Serial Port2
: 378H
: COM1
: COM2
: Enabled
•
L2 Cache Update Policy
The default value is Write Back.
Write Back
L2 Cache Write Back Operation.
Write Through
L2 Cache Write Through Operation.
NOTE: The cacheable DRAM Region is different for above two Cache Update
Policy.
L2 CACHE
Write Back
Write Through.
256 KB
32 MB
64 MB
512 KB
64 MB
128 MB
1 MB
128 MB
160 MB
•
Cache Wait / 1 = 66, 0=60 MHz
The default value is 0 Wait.
0 Wait
For 60 MHz CPU speed.
1 Wait
For 66 MHz CPU speed.
•
DRAM Timing Option
The default value is Normal.
Fast
For 60 ~ 70 ns DRAM.
Normal
For 70 ns DRAM.
Slow
For 70 ~ 80 ns DRAM.
