Pentek 52791, Getting Started Manual

Page: 7 / 14

Model 52791 Getting Started Guide Page 7
Rev. 1.0
Before You Begin:
Consider the Product’s Options
Timing and Synchronization
The following timing and synchronization options are available for the Model 52791
VPX board’s A/D converters. For more information, refer to the
Model 71791 Operating
Manual.
• External sample clock: Received from the front panel SSMC connector labeled EXT
CLK . The external clock signal must be a sine wave or square wave of +0 dBm to +12
dBm, with a frequency range from 10 to 200 MHz. This input is enabled using the
Sync Bus Control Register 1 CLK SEL bits. The clock source selected by these bits is
input to a CDCM7005 Clock Synthesizer that generates separate output clocks, each
programmable as sub − multiples of the input frequency. One of the CDCM7005
output clocks (Y0) provides ADC timing.
NOTE: Ensure that the ADC clock never exceeds the ADS5463 (or ADS5474) rated
clock speed during any change of frequency with the input clock signal.
• Onboard crystal oscillator : Alternately, the sample clock can be sourced from an
onboard programmable voltage − controlled crystal oscillator (VCXO).
•
26 − pin sync bus front panel connector
: This connector (labeled SYNC/GATE )
provides clock, sync, and gate input/output pins for the Low − Voltage Positive
Emitter − Coupled Logic (LVPECL) Sync Bus. When the Model 71791 is a bus Master,
these pins output LVPECL Sync Bus signals to other slave units. When the 71791 is a
bus Slave, these pins input LVPECL signals from a bus Master. This connector also
accepts two Low − Voltage TTL (LVTTL) Gate/Sync inputs. The mating 26 − pin
connector is Pentek part # 353.02607 (Pentek Model 2140 − 998). For a description of
the SYNC/GATE connector pin configuration, see the Model 71791 Operating Manual .
NOTE:
The LVTTL
GATE/TRIG
and
SYNC/PPS
signals are 5V tolerant but they
must NOT have any negative voltage applied. They are terminated with a
392 − Ohm resistor to 3.3V and a 392 − Ohm resistor to ground.
NOTE:
When connecting LVPECL Sync Bus pins to additional Model 71791
modules, the LVPECL pins on the LAST unit must be terminated. Pentek
includes a terminating board, Model 2140 − 999, with your shipment for
this purpose.
•
External trigger input:
The front panel has one SSMC coaxial connector, labeled
TRIG
, for input of an external trigger or gate signal. The external trigger signal must
be an LVTTL signal. The trigger input can be used as a gate or trigger for A/D signal
processing using the GATE A/B RCV SRC bits of Sync Bus Control Register 2 GATE
A/B TTL SRC bits.
NOTE: The front panel TRIG input is 5V tolerant but it must NOT have any
negative voltage applied. It is terminated with a 392 − Ohm resistor to 3.3V
and a 392 − Ohm resistor to ground.