5.7.3. Clock limitations
To visit the particular changes of the tested signals, we hope to use higher
sampling velocity, but this would greatly increase the data amount in the memory.
Besides, sometimes the tested signal is single or occasional and is included in
the long data stream. To effectively capture them, we must lengthen the time of
the sampling as we can; thus the data stored in the memory will be greater. But
the space of the high-speed memory is limited, to solve this problem; the
instrument sets two external clocks’ logic "and" and logic "or" which is limiting an
external clock using anther one. For example, select the logic "and" of two
external clocks as the sampling clock, use high level of the external clk1 as the
limit condition, only when external clk1 is a high level, the sampling
clk2
can be
opened, the sampling can run, in other times the
clk2
is shut down and cannot
sample. If set limit conditions suitable, it can ensure that not only effectively
capture the signals one interested in, but also save the space of the memory.
Using
【
Time/State
】
key can select limitation mode in cycle: the logic “and” and
logic “or” of external clock
clk1
and
clk2
.
5.7.4. Sampling cycle
The logic analyzer captures data on the hop edge of the sampling clock; the data
between two hop edges is ignored. If choose longer sampling cycle, the fast-
changing sections of input signals will be missed, then the displayed waveforms
will have serious distortion compared with the true waveforms of input signals
both in amplitude and time, even invisible. One should use shorter sampling cycle
in order to observe the particular changes of the tested signals, that is, to
increase the sampling rate.
Generally speaking, the sampling cycle should be less 3-5 times than the
narrowest pulse width of the tested signals. In other words, even the narrowest
pulse of the tested signals should include three sampling points at least, which
can truly reflect input signals’ change as time.
The instrument uses internal clock in the time sampling, and clock cycle can be
set. Press
【
system
】
to select parameter pattern-clk and input the clock cycle
value with decimalization numbers 0~9, its unit is ns, resolution is 10ns, the last
number on the right has no use. The minimum cycle value is 10 ns; the maximum
value is 999999990ns, approximate to 1s. When code generator’s clock is
changed, waveform display’s change is visible. The default setting of the clock
cycle is 10 ns, that is to say, the highest sampling velocity is 100MHz.
The instrument uses the external clock cycle in state sampling; the sampling
cycle can’t be changed optionally, one needs to select the suitable signals as the
sampling clock according to the state of the tested signals.
5.7.5. Sampling phase
The logic analyzer uses sampling clock’s rising edge for data obtaining, but in
state sampling using external clock, due to “synchronous sampling”, sometimes
should choose clock’s function edge reasonably according to logic relation
between signal and system clock of tested system. For instance, various logic
levels change in system clock’s rising edge, if samples using rising edge, various
logic level is in changing then and the time is not consistent strictly, so sampling
data may be wrong. If choose falling edge, all logic levels are just in stable state,
sampling date won’t be wrong.
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