Partner PT-1630, Sevice Manual

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15
CPU Configuration
Hyper-threading
This item enables or disables for Windows XP and Linux (OS optimized for Hyper-Threading Technology)
and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When setting this item
“Disabled” only one thread per enabled core is enabled. Options: Enabled (Default) / Disabled
Active Processor Cores
This item sets number of cores to enable in each processor package. Options: All (Default) / 1 / 2 / 3
Limit CPUID Maximum
When the computer is booted up, the operating system executes the CPUID instruction to identify the
processor and its capabilities. Before it can do so, it must first query the processor to find out the highest input
value CPUID recognizes. This determines the kind of basic information CPUID can provide the operating
system. Options: Disabled (Default) / Enabled
Execute-Disable Bit
XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS
(Windows Server 2003 SP1, Windows XP SP2, SuSE Linux 9.2, RedHat Enterprise 3 Update 3.). Options:
Enabled (Default) / Disabled
Intel Virtualization Technology
Virtualization Technology can virtually separate your system resource into several parts, thus enhance the
performance when running virtual machines or multi interface systems. Options: Disabled (Default) / Enabled
Hardware Prefetcher
The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data
and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This
reduces the latency associated with memory reads. Options: Enabled (Default) / Disabled
Adjacent Cache Line Prefetch
The processor has a hardware adjacent cache line prefetch mechanism that automatically fetches an extra
64-byte cache line whenever the processor requests for a 64-byte cache line. This reduces cache latency
by making the next cache line immediately available if the processor requires it as well. Options: Enabled
(Default) / Disabled
Figure 2.7 CPU
Configuration