Panasonic KX-TVM200E, Service Manual

Page: 38 / 164

SH-CPU interface terminal (interrupt terminal)
N_IVDC_INT input "L"Act Interrupt signal (iVDC)
N_VB_INT input "L"Act Interrupt signal (VB)
N_CDHDL_INT input "L"Act Interrupt signal (DSP)
N_WE input "L"Act Interrupt signal (Cch, HDLC)
External device control terminal (general-purpose port)
GPIO6 - GPIO1 inout - General-purpose I/O port
External device control terminal (external chip select)
N_GCS1 output "L"Act General-purpose chip select (area where wait number setting is
possible)
N_LAN_CS output "L"Act External chip select (LAN)
N_USB_CS output "L"Act External chip select (USB)
External device control terminal (HDD interface)
N_IDCS0 input "L"Act IDE0 chip select
N_IDCS1 input "L"Act IDE1 chip select
External device control terminal (DSP)
HBIL output - Byte select signal
HCNTL1 - HCNTL0 output - Register select signal
N_DSP_DS12 - N_DSP_DS1 output "L"Act DSP chip select signal (12 devices)
DSP_RW output - Chip select signal (Area 5 high-order byte)
N_DSP_GATE output "L"Act Chip select signal (Area 6 low-order byte)
DSP_HRDY input “H"Act "Read strobe"
N_DSP_HINT12 -
N_DSP_HINT1 input "L"Act Write strobe
External device control terminal (DPT (ECO) )
N_ECO_CS12 - N_ECO_CS1 output "L"Act ECO chip select signal (12 devices)
N_ECO_RE output "L"Act ECO read enable
N_ECO_WE output "L"Act ECO write enable
N_ECO_GATE output "L"Act ECO data bus enable signal
N_ECO_WAIT input "L"Act ECO wait signal
SRAM interface terminal
N_MCS2 - N_MCS1 output "L"Act SRAM chip select signal
N_MWE output "L"Act SRAM write enable signal
N_MOE output "L"Act SRAM output (read) enable signal
MA18 - MA0 output - SRAM address bus
MD15 - MD0 In/out - SRAM data bus
McBSP0 timing control terminal
M02M output - 2.048MHz, McBSP0 transfer clock
M0FS12 - M0FS1 output - McBSP0 frame signal
McBSP1 timing control terminal
M18M output - 8.192MHz, McBSP1 transfer clock
M1FS12 - M1FS1 output - McBSP1 frame signal
LHWSEL output - HW select signal
VM-Link interface terminal
SHW_CLK inout posedge VM-Link timing clock
SHW_FH inout - VM-Link frame head pulse
SHW_UHW1 output - VM-Link upstream data
SHW_DHW1 input - VM-Link downstream data
McBSP0 data (VM-Link bridge)
LDHW_D input - Voice data output to DSP
LUHW_D output - Voice data input from DSP
McBSP1 data
M1DX output - Output of compressed voice data to DSP
M1DR input - Input of compressed voice data from DSP
HDLC outside connection terminal
DPT_CLK input posedge DPT transfer clock
DPT_SYNC input - DPT frame pulse
I_DPTHW input - HDLC input data
O_DPTHW output - HDLC output data
Cch interrupt
OEP0 input Fall Cch frame signal. Detects the falling edge.
OSX input "H"Act Highway on which Cch data is carried.
Mode terminal and user test terminal
MODE1 - MODE0 input - Mode select signal. The state of this terminal can be read from the CPU
through the iVDC register.
38
KX-TVM200E / KX-TVM200NE