Panasonic KX-TVM200E, Service Manual

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McBSP2
For this DSP, McBSP2 is unassigned and used as general-purpose I/O. Depending on the slots installed, the DSP must
recognize which channel it now falls under. Therefore, the serial communication function of McBSP2 is disabled, and DR,
CLKS, FSR and CLKR are used as general-purpose input ports to discriminate 12 types of channels with these four bits.
Table: Channel Identification Bit Assignment
Pin No. Ch1
Ch2 Ch3
Ch4 Ch5
Ch6 Ch7
Ch8 Ch9
Ch10
Ch11
Ch12 Ch13
Ch14 Ch15
Ch16 Ch17
Ch18 Ch19
Ch20 Ch21
Ch22 Ch23
Ch24
42 CLKR 0 1 0 1 0 1 0 1 0 1 0 1
44 FSR 1 1 0 0 1 1 0 0 1 1 0 0
47 DR 0 0 1 1 1 1 0 0 0 0 1 1
49 CLKX 0 0 0 0 0 0 1 1 1 1 1 1
CLKR signals for the two DSPs installed in the unit are set and fixed as follows: The DSP A: CLKR = 0, DSP B: CLKR = 1.
Depending on the slots to be installed, FSR, DR and CLKX are dynamically set.
DX pins are used as output pins for the signals to control LED that shows the status of DSP.
At the time of Power ON normal: DX=High, Err, and at the time of Power DOWN: DX=Low.
The remaining pin FSX must be kept capable, as input, of reading the status from CPU.
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HPI-8
The HPI-8 is controlled directly by the CPU, and performs command settings from the CPU to the DSP, FIFO-style command
sending and receiving such as DSP status reads, and DSP program downloads on system startups or software updates.
Program downloads are carried out through the HPI-8 on system startup by directly writing to the DSP´s on-chip RAM from the
host CPU. Upon DSP startup it is in HPI boot mode.
(1) Host Interface
Between the DSP and the host CPU, DSP on-chip RAM area is accessed through the HPI. The CPU sets the DSP´s registers,
and the DSP exchanges status information and various data with the CPU.
The connection between the DSP´s HPI external interface pin and the host CPU is shown below.
There can be as many as 12 on-board DSP´s. The interrupt signals from 12 DSP´s are sent to the HPI control interface of the
ASIC. Through this signal, an interrupt flag is asserted to the appropriate channel of the HPI interrupt register in the ASIC. At
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KX-TVM200E / KX-TVM200NE