Panasonic KX-TVM200E, Service Manual

Page: 37 / 164

6.1.4. Control Block (ASIC)
The system uses an ASIC called iVDC (Intelligent Voice & Peripheral Device Controller), which comprises the voice processing
engine of the PCC voice mail system, run in combination with an SH microprocessor and TI DSPs. This ASIC allows the
sending and receiving of 24 channels of audio serial data with 12 DSPs and enables data exchange with the HDD through
buffer memory. Necessary logic is imbedded to control other peripheral devices, HDLC, and VM-Link interfaces.
Module in iVDC and Function
Module Name Function
Serial Communication Clock Module Generates bus timing of three types of McBSP0 based interfaces (DPT, APT, VM-Link).
Generates bus timing of McBSP1 based interfaces.
VM-Link Interface Module PBX interface function and bridge function with McBSP0.
VM-Link Interface Module Communicates with DSP through McBSP1. Sends and receives the compressed voice data. Controls
voice data by the voice buffer interrupt.
HDLC Module HDLC function consisting of serial packet switching managing Bch and Dch HDLC and their host
points.
SRAM Interface Module Manages timing of SRAM for external connection voice buffer.
Host CPU Interface Module Access to the CPU control register group, voice buffer access, external device access control,
addressing of external devices such as DSP, ECO, LAN, and USB.
Cch Interrupt Control Module Cch interrupt function during DPT.
DSP Control Module Manages and controls DSP interrupt.
iVDC Terminal Name and Number
Terminal Name Number of Terminals
System Terminal 2
SH-CPU Interface Terminal (Access Control Terminal) 47
SH-CPU Interface Terminal (Interrupt Terminal) 4
External Device Control Terminal (General-purpose Port) 6
External Device Control Terminal (External Chip Select) 3
External Device Control Terminal (HDD Interface) 2
External Device Control Terminal (DSP) 30
External Device Control Terminal (DPT (ECO) ) 16
SRAM Interface Terminal 39
McBSP0 Timing Control Terminal 13
McBSP1 Timing Control Terminal 14
VM-Link Interface Terminal 4
McBSP0 Data (VM-Link Bridge) 2
McBSP1 Data 2
HDLC External Connection Terminal 4
Cch Interrupt 2
Mode Terminal and User Test Terminal 3
JTAG Terminal 5
iVDC Specification
Development code name iVDC
Wafer manufacturer Fujitsu
ASIC specification 0.35 µm Embeded Cell Arrays
Number of pins 256
Power-supply voltage +3.3V
Package QFP
Operating frequency 65.536MHz for logics and PCM clocks
Terminal Descriptions
System Terminal
N_PRST input "L"Act Power-on reset signal. Asynchronous input for system reset.
SYSCLK input posedge System clock. 65.536MHz
SH-CPU interface terminal (access control terminal)
N_IVDC_CS input “L"Act Chip select signal (Area 4:iVDC)
N_CE1A input "L"Act Chip select signal (Area 5 low-order byte)
N_CE2A input "L"Act Chip select signal (Area 5 high-order byte)
N_CE1B input "L"Act Chip select signal (Area 6 low-order byte)
N_RD input “L"Act "Read strobe"
N_WE input "L"Act Write strobe
RD_NWR input "L"Act Read/write status
N_WAIT output "L"Act Wait signal
LA22 - LA1 input - CPU address input
LD15 - LD0 inout - CPU data bus
37
KX-TVM200E / KX-TVM200NE