Issue 1, Section 150-231-164
Revision 04
Page 3
payloads of the HDSL channels. The HLU-231, List 6D,
allocates the DSO time slots according to the version of
HRU-412 to which it is connected. Older version HRUs
require the odd DSO time slots allocated to channel 1
and the even DSO time slots to channel 2. Newer
versions allocated DSO time slots 1 through 12 to
channel 1, and time slots 13 through 24 to channel 2.
The 8 kbps frame bits of the DS1 stream are included on
both HDSL channels. The two formatted HDSL
channels are passed to the HDSL transceivers which
convert them to 2B1Q format on the HDSL lines. The
2B1Q line code is designed to operate in a full-duplex
mode on unconditioned pairs. The transceiver echo
canceler and adaptive equalizer receive the signal from
the remote end in the presence of impairments and
noise on the copper pairs.
3.04
The received HDSL channels are processed by
the transceiver and then passed on to the HLU-
231 List 6D multiplexer module. The multiplexer
provides frame synchronization for each of the two
HDSL channels. The multiplexer and HDSL
transceivers work under control of the HLU-231 List 6D
microprocessor and compensate for data inversions
caused by tip-ring reversals and for channel swaps
caused by pair reversals. The HiGain system allows for
tip-ring or pair reversals, but does not tolerate split pairs.
By synchronizing to the Frame Sync Word (FSW) of
each channel, the multiplexer can reconstruct the
original 1.544 Mbps DS1 stream from the payloads of
the two HDSL channels. The CRC fields on the HDSL
streams allow the HLU-231 List 6D to determine if errors
are present on the channel due to excessive
impairments on the HDSL pairs, or due to excessive
impulse or crosstalk noise.
3.05
The multiplexer removes data link messages
from the HDSL channels and passes them to
the microprocessor. This mechanism allows operations
messages and status to be exchanged between the
HLU-231 List 6D and the HRU-412 remote unit.
3.06
The reconstructed HDSL data channel is
buffered in a first-in-first-out buffer (FIFO) within
the multiplexer. A frequency synthesizer in conjunction
with the FIFO regulates the output bit rate and
reconstructs the DS1 clock at the exact rate received
from the remote end. The HiGain system operates at
DS1 rates of 1.544 Mbps with up to ±200 bps of offset.
3.07
A DSX-1 interface driver converts the DS1
channel to an Alternate Mark Inversion (AMI) or
Binary Eight Zero Substitution (B8ZS) format. The DSX-
1 equalizer is programmable to five different lengths as
determined by the distance between the HLU-231 List
6D and the DSX-1 interface. This provides CB-119
specification-compliant pulses at the DSX-1 interface
over a range of 0-655 feet of ABAM-specification cable.
Figure 2. HLU-231, List 6D Block Diagram. PairGain’s HDSL technology provides full-duplex services at standard T-1 rates over
copper wires between an HLU and an HRU, which comprise one HiGain system.
