![PairGain 150-1217-03 Manual Download Page 5](http://html1.mh-extra.com/html/pairgain/150-1217-03/150-1217-03_manual_747319005.webp)
Section 150-611-103
Revision 01
Page 5
7.03
The HLU-611 contains a demultiplexer that
generates a 1568 kb/s data stream. The
data stream contains VHDSL frames that are
nominally 9408 bits (6 milliseconds) in length. The
VHDSL frames contains a 14 bit Frame Sync Word
(FSW), 6 bit Cyclic Redundancy Check (CRC), 21
bit operations channel and DS1 payload.
7.04
The formatted VHDSL channel is passed to
the VHDSL transceiver which converts it to
a 2B1Q format on the VHDSL line. The 2B1Q line
code is designed to operate in a full-duplex mode on
one unconditioned pair. The transceiver’s echo
canceler and adaptive equalizer receive the signal
from the remote end in the presence of impairments
and noise on the copper pair.
7.05
The received VHDSL channel is processed
by the transceiver and then passed on to the
HLU-611 multiplexer module. The multiplexer
provides frame synchronization for the VHDSL
channel. The multiplexer and VHDSL transceiver
work under control of the HLU-611 micro controller
and compensate for data inversions caused by tip-
ring reversals. By synchronizing to the FSW of the
VHDSL channel, the multiplexer can reconstruct the
original 1.544 Mb/s DS1 stream from the VHDSL
channel. The CRC fields on the VHDSL streams
allow the HLU-611 to determine if errors are present
on the channel due to excessive impairments on the
VHDSL pairs or due to excessive impulse or
crosstalk noise.
7.06
The multiplexer removes data link
messages
from the VHDSL channel and
passes them to the micro controller. This
mechanism allows operations messages and status
to be exchanged between the HLU-611 and the
HRU-612 remote unit.
7.07
The reconstructed VHDSL data channel is
buffered in a first-in-first-out buffer (FIFO)
within the multiplexer. A frequency synthesizer in
conjunction with the FIFO regulates the output bit
rate and reconstructs the DS1 clock at the exact
rate received from the remote end. The HiGain-2
system operates at DS1 rates of 1.544 Mbs with up
to ±200 bits/second of offset.
7.08
A DSX-1 interface driver converts the DS1
channel to an AMI or B8ZS format. The
DSX-1 equalizer is programmable to 5 different
lengths as determined by the distance between the
HLU and the DSX-1 interface. This provides CB-
119 compliant pulses at the DSX-1 interface over a
range of 0-655 feet of ABAM cable.
7.09
The HLU-611 contains 2 separate power
converters. The main power supply
converts -48V local battery to logic power for the
HLU-611 circuits. The line power supply converts
the -48V battery to a -170 Vdc feed that provides
loop power feed on the cable pair to the HRU Unit.
The line power supply can be turned on or off by the
micro controller and is automatically shut down in
the presence of line short circuits or micro controller
failure.
7.10
The three most important power demands of
an HLU-611 on the shelf power supply are
its maximum power consumption, its maximum
power dissipation and its maximum current drain.
These three parameters for the HLU-611, on a per
slot and per shelf basis, are as follows:
Maximum Power Dissipation:
•
Per Slot = 7.0 Watts
•
Per Shelf =91 Watts
Maximum Power consumption:
•
Per Slot = 16 Watts
•
Per Shelf =208 watts
Maximum Current Drain:
•
Per Slot = 0.376 Amps
•
Per Shelf =4.9 Amps.
Note that the worse case conditions under which
these parameters were measured include a 7,500 ft.
# 26 AWG loop, 60 mA. of CPE current, a fully
loaded 13 slot shelf, and a 42.5 V shelf battery
voltage.
7.11
The Maximum Power Dissipation measures
the power that is converted into heat build
up within the unit. It contributes to the total heat
generated in the space around the unit. It is used to
determine the maximum number of fully loaded
shelves per bay that does not exceed the maximum
allowable power dissipation density in Watts/sq. ft.