22 9710 VCA
000216
ADSR Modulator (schematic above)
The output of the ADSR, at J7, is the output of a voltage follower (IC7:A) that reads the voltage on
capacitor C16. The rest of the circuit controls the charging and discharging of this capacitor.
The cross-connected transistor pair Q8 and Q9 form a bistable circuit and when power is first applied, the
circuitry settles into a stable state where Q8 is off and Q9 is on. The high collector voltage on Q8 holds
Q11 on and consequently C16 is held in a discharged state by R99 and R113. The initial state of two
other bistable elements, comparators w/hysterisis built around IC7:C and IC7:D, are useful to keep in
mind also, IC7:C is high and IC7:D is low.
A Gate input toggles the Q8/Q9 bistable and the now low voltage at Q8's collector turns Q11 off. Q9's
collector voltage is now high and the emitter follower Q10 buffers this voltage and provides the current
necessary to charge C16. The ADSR output begins to rise at a rate set by the Attack control R110. Also,
the Gate input is coupled by C23 and R120 to the base of Q15 turning this transistor on briefly which
resets the IC7:C comparator to a low output state.
As the voltage on C16, and consequently the output, increases it will at some point exceed the Sustain
level and IC7:D will switch from low to high but this simply prepares the circuit for the Decay phase
which will happen later and produces no effect at this time. When the voltage on C16 reaches the peak
value of 10V., IC7:C changes state from low to high marking the end of the Attack phase and the
beginning of Decay.
D5 and D6 along with R100 form a simple "and" gate and since both comparator outputs are now high the
gate's output is high. The resulting current flow through R106 turns on Q12 which begins to discharge
C16 at a rate determined by the Decay control R112. But notice that the output does not decay on a path
that takes it to ground but rather to the Sustain voltage at the emitter of Q13, which is an emitter follower
that buffers the voltage from the wiper of the Sustain control and provides the current for discharging
C16. When the capacitor voltage is the same as Q13's emitter voltage no more current will flow through
Q12 and discharging stops. As long as the Gate remains high this is a stable state and the ADSR output
holds at the Sustain level.
When the Gate goes low, Q8 can turn off so the Q8/Q9 bistable is reset. When Q8's collector voltage goes
high it turns on Q11 and consequently C16 continues discharging from the Sustain voltage at a rate set by
the Release control R113 until it is fully discharged or the Gate once again goes high.
DESIGN ANALYSIS
