9710 VCA 21
000216
ADSR
ADSR output. A 0 - 10V peak output function with
Attack, Decay, Sustain and Release phases.
The arrow shows that this output normals to CVa. Plugging
into this output for external use DOES NOT interrupt the normal.
Trigger input. This AC coupled input cause the
ADSR to generate the Attack and Release phases
of its output function in response to the leading edges of 4V to
15V positive pulses.
Gate input. A 4 to 15V positive voltage applied to this input starts the ADSR
function. After an initial Attack phase to a peak and Decay to a Sustaining level
that is stable as long as the Gate is present, the Release phase is generated when the gate
falls to zero.
Attack control. This panel control sets the rate at which the ADSR function increases during
the Attack phase. Clockwise rotation of the control slows the rate which is variable from
500uS to as long as 10 seconds.
Decay control. Sets the rate at which the ADSR function falls from the peak reached at the
end of the Attack phase to the level set by the Sustain control. There is some interaction with
the Sustain control with a given setting of Decay producing longer times when Sustain is set
to a low level. Time is variable from 2mS (fully CounterClockWise) to about 7 seconds (fully
ClockWise)
Sustain control. Sets the level that the ADSR function falls to at the end of the Decay phase.
Sustain voltage is variable from 0V (CCW) to 10V (CW).
Release control. Sets the rate at which the ADSR function falls from the Sustain level back to
0V output. Time is variable from 2mS (CCW) to about 7 seconds (CW).
ADSR - Cycle. When set to
Cycle the ADSR self-triggers
for an LFO function.
The block diagram shows general
signal flow and other details of the
normalization design.
