DDS VFO 2 Construction Manual – Issue 1
Page 24
10
N
OTES
10.1
O
VERCLOCKING
The AD9834 has been shown to operate effectively at clock rates much higher than the
manufacturer’s specifications. The Firmware allows for 50MHz, 80MHz and 100MHz master
oscillator frequencies and can be selected in configuration.
1.
While experiments show that the DDS chip can operate at higher clock rates,
they are outside the manufacturers published specifications and any
resulting problems are the responsibility of the kit builder.
2.
If the master clock is changed on the PCB and the configuration is not
updated the output frequency will be different to the displayed frequency.
3.
If an output frequency of greater than 10MHz is desired the output LPF will
need component changes.
10.2
DDS
OUTPUT
The output of the DDS LPF is DC coupled and does not include a series capacitor. If using the
DDS VFO other than with the MST you may need to use a series coupling capacitor between the
DDS VFO LPF and input of the other circuit.
10.3
F
REQUENCY RANGE
The DDS VFO was designed to be used as digital VFO. The minimum range allowed by the
current firmware is 10KHz. The upper frequency range is not limited by the firmware, but there
is a practical limit set by the hardware. The AD9834 is clocked by a 50MHz master clock and the
maximum usable frequency is 1/4 of this or 12.5MHz. Also the DDS VFO hardware incorporates
a LPF with a 10MHz cutoff frequency and any frequencies higher than this will be greatly
attenuated.
The DDS VFO does not limit operation beyond the amateur bands. It is up to the user
to ensure they do not transmit outside their frequency band allocation.
10.4
LCD
The DDS VFO operates best with a backlit display. The characters are bright and clear and
readable in dim environments. The backlight does consume extra current and if minimizing
current consumption is a priority then a non-backlit type can be substituted for the supplied
LCD. In this case resistor R9 can be left off the board, although leaving it in will not cause any
issues. If an LCD with backlight is used, but is not the same as supplied in the kit, the backlight
may require a different value of current limiting resistor. Check the LCD data sheet before
applying power to determine the correct resistor value and change R9 if needed.
A non-backlit display will also not be as deep and this needs to be taken into account when
mounting to the front panel.
10.5
F
IRMWARE UPGRADES
The PCB contains a functioning 6 pin ISP header to allow future firmware upgrades.
Summary of Contents for DDS VFO 2
Page 1: ...DDS VFO 2 Construction Manual Issue 1 Page 1 DDS VFO 2 CONSTRUCTION MANUAL ...
Page 7: ...DDS VFO 2 Construction Manual Issue 1 Page 7 Figure 1 CPU ...
Page 8: ...DDS VFO 2 Construction Manual Issue 1 Page 8 Figure 2 DDS generator ...
Page 9: ...DDS VFO 2 Construction Manual Issue 1 Page 9 Figure 3 LCD Rotary Encoder and Power Supply ...
Page 14: ...DDS VFO 2 Construction Manual Issue 1 Page 14 Figure 4 Component overlay ...