LTDVE8CH-20 – INSTRUCTION MANUAL
33
generator 16
91
GEN_DLY_CNT15
RW 0-
1023
Pulse delay setting for generator 16
92
GEN_WDT_BASE15
RW 0-3
Pulse width time base selector for
generator 16
93
GEN_WDT_CNT15
RW 1-
1023
Pulse width setting for generator 16
94
OUTPUT_SEL_HI0
RW 0-511 High order byte of setting for LD1 output
multiplexer
95
OUTPUT_SEL_LO0
RW 0-
65535
Low order byte of setting for LD1 output
multiplexer
96
OUTPUT_SEL_HI1
RW 0-511 High order byte of setting for LD2 output
multiplexer
97
OUTPUT_SEL_LO1
RW 0-
65535
Low order byte of setting for LD2 output
multiplexer
98
OUTPUT_SEL_HI2
RW 0-511 High order byte of setting for LD3 output
multiplexer
99
OUTPUT_SEL_LO2
RW 0-
65535
Low order byte of setting for LD3 output
multiplexer
100
OUTPUT_SEL_HI3
RW 0-511 High order byte of setting for LD4 output
multiplexer
101
OUTPUT_SEL_LO3
RW 0-
65535
Low order byte of setting for LD4 output
multiplexer
102
OUTPUT_SEL_HI4
RW 0-511 High order byte of setting for LD5 output
multiplexer
103
OUTPUT_SEL_LO4
RW 0-
65535
Low order byte of setting for LD5 output
multiplexer
104
OUTPUT_SEL_HI5
RW 0-511 High order byte of setting for LD6 output
multiplexer
105
OUTPUT_SEL_LO5
RW 0-
65535
Low order byte of setting for LD6 output
multiplexer
106
OUTPUT_SEL_HI6
RW 0-511 High order byte of setting for LD7 output
multiplexer
107
OUTPUT_SEL_LO6
RW 0-
65535
Low order byte of setting for LD7 output
multiplexer
108
OUTPUT_SEL_HI7
RW 0-511 High order byte of setting for LD8 output
multiplexer
109
OUTPUT_SEL_LO7
RW 0-
65535
Low order byte of setting for LD8 output
multiplexer