opto engineering LTDVE8CH-20, Instruction Manual

Page: 30 / 81

LTDVE8CH-20 – INSTRUCTION MANUAL
29
3 FPGA_VERSION R 0-
65535 FPGA firmware version
4 BOARD_VERSION R 0-
65535 Board version
5 OSC_PERIOD RW 10-
1000
Period of the internal oscillator
6 FILTER_SEL0 RW 0-6 Filter setting for input TR1
7 FILTER_SEL1 RW 0-6 Filter setting for input TR2
8 FILTER_SEL2 RW 0-6 Filter setting for input TR3
9 FILTER_SEL3 RW 0-6 Filter setting for input TR4
10 FILTER_SEL4 RW 0-6 Filter setting for input TR5
11 FILTER_SEL5 RW 0-6 Filter setting for input TR6
12 FILTER_SEL6 RW 0-6 Filter setting for input TR7
13 FILTER_SEL7 RW 0-6 Filter setting for input TR8
14 INPUT_SEL0 RW 0-511 Setting of input multiplexer 1
15 INPUT_SEL1 RW 0-511 Setting of input multiplexer 2
16 INPUT_SEL2 RW 0-511 Setting of input multiplexer 3
17 INPUT_SEL3 RW 0-511 Setting of input multiplexer 4
18 INPUT_SEL4 RW 0-511 Setting of input multiplexer 5
19 INPUT_SEL5 RW 0-511 Setting of input multiplexer 6
20 INPUT_SEL6 RW 0-511 Setting of input multiplexer 7
21 INPUT_SEL7 RW 0-511 Setting of input multiplexer 8
22 INPUT_SEL8 RW 0-511 Setting of input multiplexer 9
23 INPUT_SEL9 RW 0-511 Setting of input multiplexer 10
24 INPUT_SEL10 RW 0-511 Setting of input multiplexer 11
25 INPUT_SEL11 RW 0-511 Setting of input multiplexer 12
26 INPUT_SEL12 RW 0-511 Setting of input multiplexer 13
27 INPUT_SEL13 RW 0-511 Setting of input multiplexer 14
28 INPUT_SEL14 RW 0-511 Setting of input multiplexer 15
29 INPUT_SEL15 RW 0-511 Setting of input multiplexer 16
30 GEN_DLY_BASE0 RW 0-3 Pulse delay time base selector for
generator 1
31 GEN_DLY_CNT0 RW 0-
1023
Pulse delay setting for generator 1